DS80C410 Maxim, DS80C410 Datasheet - Page 96

• Manufacturer Part Number: DS80C410
• Description: The DS80C410/DS80C411 network microcontrollers offer the highest integration available in an 8051 device
• Manufacturer: Maxim

Table 26. Interrupt Summary
Unless marked, all flags must be cleared by the application software.
Note 1: Cleared automatically by hardware when the service routine is entered.
Note 2: If edge-triggered, the flag is cleared automatically by hardware when the service routine is entered. If level-triggered, the flag follows the
Note 3: The global 1-Wire interrupt-enable bit (EOWMI) and individual 1-Wire interrupt source enables are located in the internal 1-Wire bus
One’s Complement Adder
The DS80C410 implements a one’s complement adder to support the Internet checksum algorithm. The adder
contains a 16-bit accumulator and is accessed through the one’s complement adder data (OCAD) SFR.
Writing two bytes to the OCAD register initiates a summation between the 16-bit accumulator and the 16-bit value
entered. When entering a new 16-bit value for summation, the MSB should be loaded first and the LSB loaded
second. The calculation begins on the first machine cycle following the second write to the OCAD register and
executes in a single machine cycle. This allows back-to-back writes of 16-bit data to the OCAD register for
summation. The carry out bit from the high-order bit of the calculation is added back into the low-order bit of the
accumulator.
Reading two bytes from the OCAD register downloads the contents of the 16-bit accumulator. When reading the
16-bit accumulator through the OCAD register, the MSB is unloaded first and the LSB is unloaded second. The 16-
bit accumulator is cleared to 0000h following the second read of the OCAD SFR.
The following is an example sequence for producing an Internet checksum for transmission.
•
•
•
INT5/OWMI
TI0 or RI0
TI1 or RI1
TI2 or RI2
NAME
WDTI
EPMI
INT0
INT1
INT2
INT3
INT4
Read OCAD twice to make certain that the 16-bit accumulator = 0000h
Write MSB of 16-bit value to OCAD
Write LSB of 16-bit value to OCAD
WPI
TF0
TF1
TF2
TF3
EAI
PFI
C0I
state of the interrupt pin.
master interrupt enable register, and must be accessed through the OWMAD and OWMDR SFRs. Individual 1-Wire interrupt source
flag bits that are located in the internal 1-Wire bus master Interrupt flag register are accessed in the same way.
External Interrupts 2–5,
Write Protect Interrupt
Ethernet Power Mode
Power-Fail Interrupt
1-Wire Bus Master,
External Interrupt 0
External Interrupt 1
Watchdog Timer
Ethernet Activity
CAN0 Interrupt
Serial Port 0
Serial Port 1
Serial Port 2
FUNCTION
Interrupt
Timer 0
Timer 1
Timer 2
Timer 3
—
VECTOR
0Bh
1Bh
2Bh
3Bh
4Bh
5Bh
6Bh
7Bh
33h
03h
13h
23h
43h
53h
73h
63h
—
NATURAL
PRIORITY
10
11
12
13
14
15
—
0
1
2
3
4
5
6
7
8
9
96 of 102
WDIF (WDCON.3)
WPIF (MCON2.7)
EPMF (BCUC.6)
PFI (WDCON.4)
RI_0(SCON0.0)
RI_1(SCON1.0)
TI_0(SCON0.1)
TI_1(SCON1.1)
TF2(T2CON.7)
TF3 (T3CM.7))
TF0 (TCON.5)
TF1 (TCON.7)
IE0 (TCON.1)
IE1 (TCON.3)
TIF (BCUC.5)
RIF (BCUC.4)
IE2 (EXIF.4)
IE3 (EXIF.5)
IE4 (EXIF.6)
IE5 (EXIF.7)
IE4 (EXIF.6)
FLAG BIT
(Note 2)
(Note 1)
(Note 2)
(Note 1)
(Note 3)
Various
EPFI (WDCON.5)
EOWMI (Note 3)
EPMIE (EIE.7)
EX2-5 (EIE.0)
ENABLE BIT
EWDI (EIE.4)
EWPI (EIE.3)
EAIE (EIE.5)
C0IE (EIE.6)
ES2 (EIE.2)
ET3 (EIE.1)
EX0 (IE.0)
EX1 (IE.2)
ES0 (IE.4)
ES1 (IE.6)
ET0 (IE.1)
ET1 (IE.3)
ET2 (IE.5)
—
—
CONTROL BIT
EPMIP (EIP.7)
PX2-5 (EIP.0)
PWDI (EIP.4)
PWPI (EIP.3)
EAIP (EIP.5)
C0IP (EIP.6)
PS2 (EIP.2)
PT3 (EIP.1)
PRIORITY
PX0 (IP.0)
PX1 (IP.2)
PS0 (IP.4)
PS1 (IP.6)
PT0 (IP.1)
PT1 (IP.3)
PT2 (IP.5)
N/A