DS89C430 Maxim, DS89C430 Datasheet
DS89C430
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DS89C430 Summary of contents
Page 1
... GENERAL DESCRIPTION The DS89C430 and DS89C450 offer the highest performance available in microcontrollers. They feature processor cores that execute instructions times faster than the original 8051 at the same crystal speed. Typical applications will experience a speed improvement up to 10x million ...
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... Input Low Current, Port 1, 2, and 3 at 0.4V Transition Current from Port 1, 2, and (Note 12) Input Leakage Current, Port 0 in I/O Mode and EA (Note 13) Input Current, Port 0 in Bus Mode (Note 14) RST Pulldown Resistance (Note 13) DS89C430/DS89C450 Ultra-High-Speed Flash Microcontrollers SYMBOL V V PFW ...
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... RST = 5.5V. Port 0 is floating during reset and when in the logic-high state during I/O mode. Note 14: This port is a weak address holding latch in bus mode. Peak current occurs near the input transition point of the holding latch at approximately 2V. DS89C430/DS89C450 Ultra-High-Speed Flash Microcontrollers to V MIN RST and V overlap, the design of the hardware makes it so this is not possible ...
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... STC3 - CLCL CLCL - 8 0. 0.5t CLCL + STC2 - 8 0. 0.5t CLCL + STC3 CLCL 1. 0.5t CLCL - CLCL CLCL DS89C430/DS89C450 UNITS MIN MAX 0 33 MHz CLCL ns STC3 CLCL CLCL ns STC3 CLCL ns STC2 - 8 CLCL ns STC2 CLCL ...
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... STC1 - CLCL CLCL + STC1 STC1 STC1 CLCL CLCL + STC1 STC1 DS89C430/DS89C450 Ultra-High-Speed Flash Microcontrollers 4-CYCLE PAGE MODE 2 NONPAGE MODE MAX MIN MAX MIN CLCL CLCL CLCL 1. CLCL 2. CLCL ...
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... STC5 STC5 - STC2 CLCL STC2 CLCL - STC2 STC2 STC2 STC2 DS89C430/DS89C450 Ultra-High-Speed Flash Microcontrollers 4-CYCLE PAGE MODE 2 NONPAGE MODE MAX MIN MAX MIN CLCL + t STC1 3. CLCL CLCL STC1 STC1 - 0. ...
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... LLPL t PXIX LLIV t LLAX Port 0 LSB MOVX t PXIZ Port 2 MSB DS89C430/DS89C450 Ultra-High-Speed Flash Micrcontrollers ” used in the AC Characteristics variable timing table is determined from the CLCL Number of External Clock Cycles per System Clock (1/t ) CLCL 1/4 1/2 Reserved 1 1024 MOVX Instruction Time t STC1 2 Machine Cycles ...
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... Figure 3. Page Mode 2 Timing XTAL1 t CLCL ALE t AVLL t AVLL2 PSEN t LLPL t PLIV PXIX t LLIV Port 0 LSB t LLAX Port 2 MSB OPCODE DS89C430/DS89C450 Ultra-High-Speed Flash Microcontrollers t LHLL t LLAX3 t LLWL t RLRH t RHDX t RLDV MOVX DATA t AVDV2 MSB LSB MSB t LHLL t AVLL3 t PLPH t LLAX3 ...
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... Rising Clock Rising Edge to Input t XHDV Data Valid Note: SM2 is the serial port 0 mode bit 2. When serial port 0 is operating in mode 0 (SM0 = SM1 = 0), SM2 determines the number of crystal clocks in a serial port clock cycle. DS89C430/DS89C450 Ultra-High-Speed Flash Microcontrollers SYMBOL t CHCX t CLCX t ...
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... XHDV R1 SERIAL PORT (SYNCHRONOUS MODE) SM2 = 0 TDX CLOCK = XTAL FREQ/12 ALE PSEN WRITE TO SBUF RXD DATA OUT TXD CLOCK TI WRITE TO SCON TXD CLOCK TO CLEAR RI RXD DATA IN TXD CLOCK R1 DS89C430/DS89C450 Ultra-High-Speed Flash Microcontrollers t XHQX XLXL XHDX ...
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... Note 19: Reset delay is a synchronous counter of crystal oscillations after crystal startup. Counting begins when the level on the XTAL1 pin meets the V criteria. At 33MHz, this time is 1.99ms. IH2 FLASH MEMORY PROGRAMMING CHARACTERISTICS (V = 4.5V to 5.5V) CC PARAMETER Data Retention Write/Erase Endurance Program/Time Erase Time DS89C430/DS89C450 Ultra-High-Speed Flash Microcontrollers SYMBOL MIN TYP t 8 CSU t 65,536 POR SYMBOL MIN TYP ...
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... P0.5 (AD5) P0.6 (AD6 P0.7 (AD7 DS89C430/DS89C450 Ultra-High-Speed Flash Microcontrollers NAME V +5V CC GND Logic Ground External Reset. The RST input pin is bidirectional and contains a Schmitt Trigger to recognize external active-high reset inputs. The pin also employs an internal pulldown RST resistor to allow for a combination of wire-ORed external reset sources not required for power-up, as the device provides this function internally ...
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... In this state, a weak pullup holds the port high. This condition also serves as an input mode, since any external circuit that writes to the port overcomes the weak pullup. When software writes any port pin, the DS89C430/DS89C450 activate a strong pulldown that remains on until either written or a reset occurs. Writing a 1 after the port has been at 0 causes a strong transition driver to turn on, followed by a weaker sustaining pullup ...
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... I/O ports. The three part numbers vary only by the amount of internal flash memory (DS89C430 = 16kB, DS89C450 = 64kB), which can be in-system/in- application programmed from a serial port using ROM-resident or user-defined loader software. For volume deployments, the flash can also be loaded externally using standard commercially available parallel programmers ...
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... Terminology The term DS89C430 is used in the remainder of the document to refer to the DS89C430 and DS89C450, unless otherwise specified. Compatibility The DS89C430 is a fully static CMOS 8051-compatible microcontroller similar in functional features to the DS87C520, but it offers much higher performance. In most cases, the DS89C430 can drop into an existing socket for the 8xC51 family, immediately improving the operation ...
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... RAM by setting the stack pointer to the desired location, although the lower bytes are normally used for working registers. I/O Ports The DS89C430 offers four 8-bit I/O ports. Each I/O port is represented by an SFR location and can be written or read. The I/O port has a latch that contains the value written by software. Counter/Timers Three 16-bit timer/counters are available in the DS89C430 ...
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... WDCON D8h SMOD_1 ACC E0h EIE E8h — B F0h EIP1 F1h — EIP0 F8h — Note: Shaded bits are timed-access protected. DS89C430/DS89C450 Ultra-High-Speed Flash Microcontrollers BIT 6 BIT 5 BIT 4 WD0 T2M T1M P1.6/INT4 P1.5/INT3 P1.4/INT2 IE4 IE3 IE2 T2MH T1MH SM1_0 SM2_0 ...
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... SADEN0 B9h SADEN1 BAh SCON1 C0h SBUF1 C1h ROMSIZE C2h PMR C4h STATUS C5h TA C7h T2CON C8h T2MOD C9h RCAP2L CAh RCAP2H CBh DS89C430/DS89C450 Ultra-High-Speed Flash Microcontrollers BIT 7 BIT 6 BIT 5 BIT ...
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... ROMSIZE feature allows software to dynamically configure the maximum address of on-chip program memory. This allows the DS89C430 to act as a bootloader for an external memory. It also enables the use of the overlapping external program spaces. The lower 128 bytes of on-chip flash memory—if ROMSIZE is greater than 0— ...
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... As illustrated in Figure 6, the DS89C430 incorporates two 8kB flash areas for on-chip program memory and 1kB of SRAM for on-chip data memory or a particular range (400–7FF) of “alternate” program memory space. The DS89C450 incorporates two 32kB flash memories. The DS89C430 uses an address scheme that separates program memory from data memory such that the 16-bit address bus can address each memory area up to maximum of 64kB ...
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... The maximum on-chip decoded address is selectable by software using the ROMSIZE feature. Software can cause the DS89C430 to behave like a device with less on-chip memory. This is beneficial when overlapping external memory is used. The maximum memory size is dynamically variable. Thus a portion of memory can be removed from the memory map to access off-chip memory and then be restored to access on-chip memory ...
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... Security Features The DS89C430 incorporates a 64-byte encryption array, allowing the user to verify program codes while viewing the data in encrypted form. The encryption array is implemented in a security flash memory block that has the same electrical and timing characteristics as the on-chip program memory. Once the encryption array is programmed to non-FFh, the data presented in the verify mode is encrypted ...
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... However, the lock bits do affect the read/write accessibility in ROM loader and parallel programming modes. In-Application Programming by User Software The DS89C430 supports in-application programming of on-chip flash memory by user software. In-application programming is initiated by writing a flash command into the flash control (FCNTL:D5h) register to enable the flash memory for erase/program/verify operations. Address and data are input into the MMU through the flash data (FDATA:D6h) register. The flash command also enables read/write accesses to the FDATA. The MMU’ ...
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... Any command written to the FCNTL during a flash operation is ignored (FBUSY = 0). To ensure data integrity, an erase command sequence should be reinitiated if an erase or program operation is interrupted by a reset. DS89C430/DS89C450 Ultra-High-Speed Flash Microcontrollers OPERATION Default state. All flash blocks are in read mode. Note: The upper bank of flash memory is inaccessible for execution unless the FC3:0 bits are in the read mode (0000b) state ...
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... When the DS89C430 is powered up and has entered its user operating mode, the ROM loader mode can be invoked at any time by forcing RST = and PSEN = 0. It remains in effect until power-down or when the condition (RST = 1 and PSEN = removed ...
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... The DS89C430 also supports a second page mode operation with a different external bus structure that provides for fast external code fetches but uses four system clock cycles for data memory access. ...
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... A basic internal memory cycle contains one system clock and a basic external memory cycle contains four system clocks for nonpage mode operation. The DS89C430 allows software to adjust the speed of external data memory access by stretching the memory bus cycle. CKCON (8Eh) provides an application-selectable stretch value for this purpose. Software can change the stretch value dynamically by changing the setting of CKCON.2– ...
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... Figure 9. Nonpage Mode, External Data Memory Access (Stretch = 1, CD1:CD2 = 10) 1st Machine Cycle XTAL1 ALE PSEN RD/WR Port 0 A MOVX Port 2 A MOVX Instruction Fetch DS89C430/DS89C450 Ultra-High-Speed Flash Microcontrollers MOVX Instruction 2nd Machine Cycle 1st Machine Cycle A INST A DATA A Memory Access Stretch = 0 MOVX Instruction 2nd Machine Cycle ...
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... The DS89C430 supports page mode in two external bus structures. The logic value of the page-mode- select bits in the ACON register determines the external bus structure and the basic memory cycle in number of system clocks ...
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... Generally, the first external memory access causes a page miss. The new page address is stored internally and is used to detect a page miss for the current external memory cycle. DS89C430/DS89C450 Ultra-High-Speed Flash Microcontrollers External Memory Cycles MOVX MOVX ...
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... Port 2 Stretch External Data Memory Cycle in Page Mode The DS89C430 allows software to adjust the speed of external data memory access by stretching the memory bus cycle in page mode operation just like nonpage mode operation. The following tables summarize the stretch values and their effect on the external MOVX memory bus cycle and the control signals’ pulse width in terms of the number of oscillator clocks ...
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... Table 9. Page Mode 1, Data Memory Cycle Stretch Values (PAGES1:PAGES0 = 10) STRETCH MD2:MD0 4X CD1, CYCLES 000 0 001 1 010 2 011 3 100 7 101 8 110 9 111 10 DS89C430/DS89C450 Ultra-High-Speed Flash Microcontrollers PULSE WIDTH (IN NUMBER OF OSCILLATOR CLOCKS) 4X CD1, CD0 = 100 CD0 = 000 0.25 0.5 0.75 1.5 1.75 3.5 2.75 5.5 3.75 7.5 4.75 9.5 5.75 11.5 6.75 13 PULSE WIDTH (IN NUMBER OF OSCILLATOR CLOCKS) ...
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... The stretched data memory bus cycle timing relationship for PAGES = 11 is identical to nonpage mode operation since the basic data memory cycle always contains four system clocks in this page mode operation. DS89C430/DS89C450 Ultra-High-Speed Flash Microcontrollers RD/WR PULSE WIDTH (IN NUMBER OF OSCILLATOR CLOCKS) 4X CD1, ...
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... Fetch ALE PSEN Port 0 Inst MOVX Port 2 LSB Addr LSB Addr MOVX Inst Fetch DS89C430/DS89C450 Ultra-High-Speed Flash Microcontrollers MOVX Instruction Inst MOVX LSB Addr LSB Addr MSB Addr Memory Access (Stretch =1) MOVX Instruction Inst LSB Addr LSB Addr MSB Addr ...
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... Fetch Interrupts The DS89C430 provides 13 interrupt sources. All interrupts, with the exception of the power fail, are controlled by a series combination of individual enable bits and a global enable (EA) in the interrupt-enable register (IE.7). Setting logic 1 allows individual interrupts to be enabled. Setting logic 0 disables all interrupts regardless of the individual interrupt-enable settings ...
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... Note 1: If the interrupt is edge triggered, the flag is cleared automatically by hardware when the service routine is vectored to. If the interrupt is level triggered, the flag follows the state of the pin. Note 2: The flag is cleared automatically by hardware when the service routine is vectored to. DS89C430/DS89C450 Ultra-High-Speed Flash Microcontrollers FLAG 0 (Highest) PFI (WDCON ...
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... Timer/Counters The DS89C430 incorporates three 16-bit timers. All three timers can be used as either counters of external events, where 1-to-0 transitions on a port pin are monitored and counted, or timers that count oscillator cycles. summarizes the timer functions. Timers 0 and 1 both have three modes of operations. They can each be used as a 13-bit timer/counter, a 16-bit timer/counter 8-bit timer/counter with autoreload ...
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... An on-chip crystal multiplier allows the DS89C430 to operate at two or four times the crystal frequency by setting the 4X/2X bit, and is enabled by setting the CTM bit to a logic 1. An additional circuit provides a clock source at divide by 1024. When used with a 7.372MHz crystal, for example, the processor executes the machine cycle in times ranging from 33.9ns (mulitply-by-4 mode) to 138.9 ...
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... POR (WDCON.6) is set to logic 1 to indicate a power-on reset has occurred, and can only be cleared by software. When the DS89C430 enters stop mode, the bandgap, reset comparator, and power-fail interrupt comparator are automatically disabled to conserve power if the BGS (EXIF.0) bit is set to logic 0. This is the lowest power mode. If BGS is set to logic 1, the bandgap reference, reset comparator, and the power-fail comparator are powered up, although in a mode that reduces their power consumption ...
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... A software reset can be initiated by writing a system reset command to the flash control SFR. The reset state is maintained for approximately 90 external clock cycles. During this time, the RST pin is driven to a logic high. Once the reset is removed, the RST pin is driven low, and operation begins from address 0000h. DS89C430/DS89C450 Ultra-High-Speed Flash Microcontrollers WD1 ...
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... RST pin does not affect the internal reset condition. Oscillator-Fail Detect and Reset The DS89C430 incorporates an oscillator-fail-detect circuit that, when enabled, causes a reset if the crystal oscillator frequency falls below 20kHz and holds the chip in reset with the ring oscillator operating. Setting the OFDE (PCON ...
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... On returning from the interrupt vector using the RETI instruction, the next address is the one that immediately follows the instruction that invoked the idle mode. Any reset of the processor also removes the idle mode. DS89C430/DS89C450 Ultra-High-Speed Flash Microcontrollers summarizes the effect of clock mode on timer operation. OSC CYCLES PER ...
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... All instructions are 100% binary compatible with the industry-standard 8051, and are only different in the number of machine cycles used for the instructions. There are some special conditions and features to be considered when analyzing the DS89C430 instruction set. Full details are available in the Ultra-High-Speed Flash Microcontroller User’s Guide. ...
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... Contact factory or replace with DS89C430 or DS89C450. 64kB x 8 64kB x 8 64kB x 8 64kB x 8 64kB x 8 64kB x 8 64kB x 8 64kB x 8 64kB x 8 ...
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... DS89C450 44 1 TQFP PACKAGE INFORMATION For the latest package outline information and land patterns www.maxim-ic.com/packages. PACKAGE TYPE PACKAGE CODE 44 TQFP C44+2 40 PDIP P40+3 40 PLCC Q44+7 DS89C430/DS89C450 Ultra-High-Speed Flash Microcontrollers 40 39 P1.0/T2 P1.1/T2EX P1.2/RXD1 P1.3/TXD1 P1.4/INT2 P1.5/INT3 29 P1.6/INT4 P1.7/INT5 28 RST P3.0/RXD0 P3 ...
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... Clarified IAP programming sequence. 060805 Added lead-free devices to Ordering Information table. Removed references to DS89C440 and/or added “Contact factory or replace with DS89C430 or 091906 DS89C450.” Added clarification to the Security Features section and Table 3 that flash security levels 1, 2, and 3 040507 should not be used when executing external code (page 22) ...