71M6531F Maxim, 71M6531F Datasheet
71M6531F
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71M6531F Summary of contents
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... Two UARTs for IR and AMR, IR driver with modulation • FLASH memory with security and in-system program update: 128 KB (71M6531D/32D) 256 KB (71M6531F/32F) • MPU XRAM • Industrial temperature range • 68-pin QFN package for 71M6531D/F pin- compatible with 71M6521, 100-pin LQFP ...
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Data Sheet 71M6531D/F-71M6532D/F 1 Hardware Description ....................................................................................................................... 10 1.1 Hardware Overview ................................................................................................................... 10 1.2 Analog Front End (AFE) ............................................................................................................. 10 1.2.1 Signal Input Pins ............................................................................................................ 10 1.2.2 Input Multiplexer ............................................................................................................ 11 1.2.3 A/D Converter (ADC) ..................................................................................................... 12 1.2.4 FIR Filter ...
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FDS 6531/6532 005 2 Functional Description ..................................................................................................................... 54 2.1 Theory of Operation ................................................................................................................... 54 2.2 System Timing Summary ........................................................................................................... 55 2.3 Battery Modes ............................................................................................................................ 56 2.3.1 BROWNOUT Mode ....................................................................................................... 57 2.3.2 LCD Mode ...................................................................................................................... 58 2.3.3 SLEEP Mode ................................................................................................................. 58 ...
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... Data Sheet 71M6531D/F-71M6532D/F 4.3.10 Other CE Parameters .................................................................................................... 95 4.3.11 CE Flow Diagrams ......................................................................................................... 95 5 Electrical Specifications ................................................................................................................... 98 5.1 Absolute Maximum Ratings ....................................................................................................... 98 5.2 Recommended External Components ....................................................................................... 99 5.3 Recommended Operating Conditions ........................................................................................ 99 5.4 Performance Specifications ..................................................................................................... 100 5.4.1 Input Logic Levels ........................................................................................................ 100 5.4.2 Output Logic Levels ..................................................................................................... 100 5.4.3 Power-Fault Comparator ............................................................................................. 100 5.4.4 Battery Monitor............................................................................................................. 100 5.4.5 Supply Current ............................................................................................................. 101 5 ...
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FDS 6531/6532 005 Figures Figure 1: 71M6531D/F IC Functional Block Diagram ................................................................................... 8 Figure 2: 71M6532D/F IC Functional Block Diagram ................................................................................... 9 Figure 3: General Topology of a Chopped Amplifier .................................................................................. 13 Figure 4: CROSS Signal with CHOP_E[1: ...
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Data Sheet 71M6531D/F-71M6532D/F Tables Table 1: Inputs Selected in Regular and Alternate Multiplexer Cycles ....................................................... 11 Table 2: ADC Resolution ............................................................................................................................. 12 Table 3: ADC RAM Locations ..................................................................................................................... 12 Table 4: XRAM Locations for ADC Results ................................................................................................ 15 Table 5: ...
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... Table 62: Useful CE Measurement Parameters ......................................................................................... 93 Table 63: CE Pulse Generation Parameters ............................................................................................... 94 Table 64: CE Calibration Parameters ......................................................................................................... 94 Table 65: CE Parameters for Noise Suppression and Code Version ......................................................... 95 Table 66: Absolute Maximum Ratings ........................................................................................................ 98 Table 67: Recommended External Components ........................................................................................ 99 Table 68: Recommended Operating Conditions ......................................................................................... 99 Table 69: Input Logic Levels ..................................................................................................................... 100 Table 70: Output Logic Levels .................................................................................................................. 100 Table 71: Power-Fault Comparator Performance Specifications ...
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Data Sheet 71M6531D/F-71M6532D/F VREF VBIAS VADC IA VA VREF MUX IB VREF_CAL VREF_DIS VB EQU MUX_ALT VBAT MUX_DIV 2.5V_NV RTCLK (32KHz) XIN OSC CKOUT_E (32KHz) XOUT RTCA_ADJ RTC RST_SUBSEC 2.5V_NV QREG PREG RTC_DAY TEMP RTC_HR RTC_DATE SENSOR RTC_MIN RTC_MO RTC_SEC ...
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FDS 6531/6532 005 VREF VBIAS IAP VADC IAN MUX VREF VA VREF_CAL IBP VREF_DIS IBN VB EQU MUX_ALT VBAT MUX_DIV 2.5V_NV RTCLK (32KHz) XIN OSC CKOUT_E (32KHz) XOUT RTCA_ADJ RTC RST_SUBSEC 2.5V_NV QREG PREG RTC_DAY TEMP RTC_HR RTC_DATE SENSOR RTC_MIN ...
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Data Sheet 71M6531D/F-71M6532D/F 1 Hardware Description 1.1 Hardware Overview The Teridian 71M6531D/F and 71M6532D/F single-chip energy meters integrates all primary functional blocks required to implement a solid-state electricity meter. Included on the chips are: • An analog front end (AFE) ...
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FDS 6531/6532 005 1.2.2 Input Multiplexer The input multiplexer supports up to four input signals that are applied to pins IA (IAP/IAN), VA, IB (IBP/IBN), and VB of the device. Additionally, using the alternate multiplexer selection, it has the ability ...
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Data Sheet 71M6531D/F-71M6532D/F The duration of each multiplexer state depends on the number of ADC samples processed by the FIR, which is set by FIR_LEN[1:0]. Each multiplexer state will start on the rising edge of CK32. The MUX_CTRL signal sends ...
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FDS 6531/6532 005 V inp V inn CROSS Figure 3: General Topology of a Chopped Amplifier It is assumed that an offset voltage Voff appears at the positive amplifier input. With all switches, as controlled by CROSS, in the A ...
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Data Sheet 71M6531D/F-71M6532D/F the number of multiplexer frames in an accumulation interval is always even. Operation with CHOP_E[1: does not require control of the chopping mechanism by the MPU while eliminating the offset for temperature measurement. In the ...
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FDS 6531/6532 005 1.3 Digital Computation Engine (CE) The CE, a dedicated 32-bit signal processor, performs the precision computations necessary to accurately measure energy. The CE calculations and processes include: • Multiplication of each current sample with its associated voltage ...
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... Pulses generated by the CE may be exported to the XPULSE and YPULSE pulse outputs. Pins DIO8 and DIO9 are used for these pulses. Generally, the XPULSE and YPULSE outputs are updated once on each pass of the CE code, resulting in a pulse frequency maximum of 1260Hz (assuming a MUX frame is 13 CK32 cycles). ...
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... CE and the MPU using a time-multiplex method. This reduces MPU wait states when accessing CE data. When the MPU and CE are clocking at maximum frequency (10 MHz), the DRAM will make up to four accesses during each 100 ns interval. These consist of two MPU accesses, one CE access and one SPI access ...
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Data Sheet 71M6531D/F-71M6532D/F For example, PRE_SAMPS[1: and SUM_CYCLES[5: will establish 2100 samples per accumulation cycle. PRE_SAMPS[1:0] = 100 and SUM_CYCLES[5: will result in the exact same accumulation cycle of 2100 samples or 833 ms. ...
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FDS 6531/6532 005 1.4 80515 MPU Core The 71M6531D/F and 71M6532D/F include an 80515 MPU (8-bit, 8051-compatible) that processes most instructions in one clock cycle. Using a 10-MHz clock results in a processing throughput of 10 MIPS. The 80515 architecture ...
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Data Sheet 71M6531D/F-71M6532D/F The 80515 writes into external data memory when the MPU executes a MOVX @Ri,A or MOVX @DPTR,A instruction. The MPU reads external data memory by executing a MOVX A,@Ri or MOVX A,@DPTR instruction (SFR PDATA provides the ...
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FDS 6531/6532 005 An alternative data pointer is available in the form of the PDATA register (SFR 0xBF), sometimes referred to as USR2). It defines the high byte of a 16-bit address when reading or writing XDATA with the instruction ...
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Data Sheet 71M6531D/F-71M6532D/F 1.4.3 Generic 80515 Special Function Registers Table 10 shows the location, description and reset or power-up value of the generic 80515 SFRs. Additional descriptions of the registers can be found at the page numbers listed in the ...
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FDS 6531/6532 005 Accumulator (ACC, A, SFR 0xE0): ACC is the accumulator register. Most instructions use the accumulator to hold the operand. The mnemonics for accumulator-specific instructions refer to accumulator as A, not ACC. B Register (SFR 0xF0): The B ...
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Data Sheet 71M6531D/F-71M6532D/F SFR Register R/W Address P0 0x80 R/W Register for port 0 read and write operations. DIR0 0xA2 R/W Data direction register for port 0. Setting a bit to 1 indicates that the corresponding pin is an output. ...
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FDS 6531/6532 005 Register SFR (Alternate Name) Address ERASE 0x94 (FLSH_ERASE) FL_BANK 0xB6[2:0] PGADDR 0xB7 (FLSH_PGADR[5:0]) 0xB2[0] 0xB2[1] FLSHCRL 0xB2[6] 0xB2[7] 0xE8[0] 0xE8[1] 0xE8[2] 0xE8[3] IFLAGS 0xE8[4] 0xE8[5] 0xE8[6] 0xE8[7] 0xF8[6:0] INTBITS 0xF8[7] (INT0 … INT6) Only byte operations on ...
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Data Sheet 71M6531D/F-71M6532D/F 1.4.5 Instruction Set All instructions of the generic 8051 microcontroller are supported. A complete list of the instruction set and of the associated op-codes is contained in the 71M653X Software User’s Guide (SUG). 1.4.6 UARTs The 71M6531D/F ...
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FDS 6531/6532 005 The feature of receiving 9 bits (Mode 3 for UART0, Mode A for UART1) can be used as handshake signals for inter-processor communication in multi-processor systems. In this case, the slave processors have bit SM20 (S0CON[5]) for ...
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... (T0 and T1 are the timer gating inputs derived from certain DIO pins, see Section cycles to recognize a 1-to-0 event, the maximum input count rate is 1/2 of the clock frequency (CKMPU). There are no restrictions on the duty cycle, however to ensure proper recognition of the state, an input should be stable for at least 1 machine cycle ...
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FDS 6531/6532 005 Table 21: Allowed Timer/Counter Mode Combinations Timer 0 - mode 0 Timer 0 - mode 1 Timer 0 - mode 2 Table 22: TMOD Register Bit Description (SFR 0x89) Bit Symbol Timer/Counter 1: If TMOD[7] is set, ...
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Data Sheet 71M6531D/F-71M6532D/F 1.4.8 WD Timer (Software Watchdog Timer) There is no internal software watchdog timer. Use the standard watchdog timer instead (see Hardware Watchdog Timer). 1.4.9 Interrupts The 80515 MPU provides 11 interrupt sources with four priority levels. Each ...
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FDS 6531/6532 005 Table 25: The IEN1 Bit Functions (SFR 0xB8) Bit Symbol – IEN1[7] Not used. – Not used. IEN1[6] EX6 = 0 disables external interrupt 6: XFER_BUSY, RTC_1SEC, WD_NROVF IEN1[5] EX6 IEN1[4] EX5 EX5 = 0 disables external ...
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Data Sheet 71M6531D/F-71M6532D/F IRCON[1] IEX2 1 = External interrupt 2 occurred and has not been cleared. – Not used. IRCON[0] TF0 and TF1 (Timer 0 and Timer 1 overflow flags) will be automatically cleared by hardware when the service routine ...
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FDS 6531/6532 005 Interrupt Enable Name Location SFR B8[3] EX4 SFR B8[4] EX5 EX6 SFR B8[5] EX_XFER 2002[0] 2002[1] EX_RTC IEN_WD_NROVF 20B0[0] IEN_SPI 20B0[4] EX_FWCOL 2007[4] 2007[5] EX_PLL † The AUTOWAKE and PB flag bits are shown in even though ...
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Data Sheet 71M6531D/F-71M6532D/F Table 34: Interrupt Priority Registers (IP0 and IP1) Register Address Bit 7 (MSB) – IP0 SFR 0xA9 – SFR 0xB9 IP1 Interrupt Sources and Vectors Table 36 shows the interrupts with their associated flags and vector addresses. ...
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FDS 6531/6532 005 ...
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... MCK ** Default state at power-up *** The maximum CKMPU frequency. CKMPU can be reduced from this rate using MPU_DIV[2:0]. † CKCE = 9.8304 MHz when CE10MHZ is set, 4.9152 MHz otherwise. The master clock, MCK, is generated by an on-chip PLL that multiplies the oscillator output frequency (CK32) by 2400 to provide approximately 80 MHz (78.6432 MHz). A divider controlled by the I/O RAM bits M40MHZ and M26MHZ permits scaling of MCK by ½ ...
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... The adjustable capacitance is approximately: The maximum adjustment range is approximately-12 ppm to +22ppm. The precise amount of adjustment will depend on the crystal properties. The adjustment may occur at any time and the resulting clock frequency can be measured over a one-second interval. ...
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... Physical Memory Flash Memory The 71M6531D and 71M6532D include 128 KB of on-chip flash memory. The 71M6531F and 71M6532F offer 256 KB of flash memory. The flash memory primarily contains MPU and CE program code. It also contains images of the CE and MPU data in RAM, as well as of I/O RAM. On power-up, before enabling the CE, the MPU copies these images to their respective locations ...
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... The 71M6531D provides 4 banks each selected by FL_BANK[1:0]. Note that when FL_BANK[1:0] = 00, the upper bank is the same as the lower bank. • The 71M6531F and 71M6532D/F provide 8 banks each selected by FL_BANK[2:0]. Table 38 illustrates the bank switching mechanism. v1.3 © 2005-2010 TERIDIAN Semiconductor Corporation ...
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Data Sheet 71M6531D/F-71M6532D/F Table 38: Bank Switching with FL_BANK[2:0] 71M6531D 71M653XF FL_BANK [1:0] FL_BANK [2:0] 000 000 001 001 010 010 011 011 100 101 110 111 Program Security When enabled, the security feature limits the ICE to global flash ...
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FDS 6531/6532 005 from OPT_TX UART OPT_TXINV OPT_TXMOD = 1.5.7 Digital I/O – 71M6531D/F The 71M6531D/F includes pins of general-purpose digital I/O. These pins are compatible with 5 V inputs (no current limiting resistors ...
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Data Sheet 71M6531D/F-71M6532D/F Table 39: Data/Direction Registers and Internal Resources for DIO 1-15 (71M6531D/F) DIO PB 1 LCD Segment – – Pin number 65 60 – – Configuration (DIO or LCD segment Data Register DIO0 = P0 (SFR ...
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FDS 6531/6532 005 1.5.8 Digital I/O – 71M6532D/F The 71M6532D/F includes pins of general-purpose digital I/O. These pins are compatible with 5 V inputs (no current limiting resistors are needed). The Digital I/O pins can be categorized ...
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Data Sheet 71M6531D/F-71M6532D/F Table 44: Data/Direction Registers and Internal Resources for DIO 40-51 (71M6532D/F) DIO 40 LCD Segment 60 Pin number 95 Configuration (DIO or LCD segment) LCD_BITMAP[63:56] Data Register Direction Register 0 = input output DIO24 and ...
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... With a minimum of 16 driver pins always available and a total of 39 driver pins in the maximum configuration, the device is capable of driving between 64 to 156 pixels of LCD display with 25% duty cycle. At eight pixels per digit, this corresponds digits ...
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... ICE interface (SEG9 to SEG11) • 43 multi-use LCD/DIO pins described in Section With a minimum of 15 driver pins always available and a total of 67 driver pins in the maximum configuration, the device is capable of driving between 60 to 268 pixels of an LCD display with 25% duty cycle. At eight pixels per digit, this corresponds to 7 ...
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FDS 6531/6532 005 Two-Pin EEPROM Interface The dedicated 2-pin serial interface communicates with external EEPROM devices. The interface is multiplexed onto the DIO4 (SCK) and DIO5 (SDA) pins and is selected by setting DIO_EEX[1:0] = 01. The MPU communicates with ...
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Data Sheet 71M6531D/F-71M6532D/F Table 48: EECTRL Bits for the 3-Wire Interface Control Read/ Name Bit Write 7 WFR W Wait for Ready. If this bit is set, the trailing edge of BUSY will be delayed until a rising edge is ...
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FDS 6531/6532 005 EECTRL Byte Written READ SCLK (output) SDATA (input) SDATA output Z BUSY (bit) Figure 13: 3-Wire Interface. Read Command. EECTRL Byte Written INT5 not issued Write -- No HiZ SCLK (output) SDATA (output) D7 SDATA output Z ...
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Data Sheet 71M6531D/F-71M6532D/F Command 11xx xxxx ADDR Byte0 ... ByteN 10xx xxxx ADDR Byte0 ... ByteN Certain I/O RAM registers can be written and read using the SPI port (see Table 50). However, the MPU takes priority over the I/O ...
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FDS 6531/6532 005 Name SPI0 SPI1 VERSION CHIP_ID TRIMSEL TRIMX TRIM SERIAL READ 8 bit CMD PCSZ 0 PSCK (From Host) PSDI (From 6531) PSDO SERIAL WRITE 8 bit CMD PCSZ 0 PSCK (From Host) PSDI ...
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Data Sheet 71M6531D/F-71M6532D/F 1.5.16 Hardware Watchdog Timer An independent, robust, fixed-duration, watchdog timer (WDT) is included V1 in the 71M6531D/F and 71M6532D/F. It uses the RTC crystal oscillator as its time base and must be refreshed by the MPU firmware ...
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FDS 6531/6532 005 1.5.17 Test Ports (TMUXOUT pin) One of the digital or analog signals listed in The function of the multiplexer is controlled with the I/O RAM field TMUX[4:0] (0x20AA[4:0]), as shown in Table 51. Mode TMUX[4:0] 0 Analog ...
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Data Sheet 71M6531D/F-71M6532D/F 2 Functional Description 2.1 Theory of Operation The energy delivered by a power source into a load can be expressed as: Assuming phase angles are constant, the following formulae apply: Real Energy [Wh] = ...
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FDS 6531/6532 005 2.2 System Timing Summary Figure 19 summarizes the timing relationships between the input MUX states, the CE_BUSY signal and the two serial output streams. In this example, MUX_DIV[3: and FIR_LEN[1: (384 CE cycles, ...
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Data Sheet 71M6531D/F-71M6532D/F 2.3 Battery Modes Shortly after system power (V3P3SYS) is applied, the part will be in MISSION mode. MISSION mode means that the part is operating with system power and that the internal PLL is stable. This mode ...
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FDS 6531/6532 005 To facilitate transition to sleep mode, which is useful when an unprogrammed IC is mounted on a PCB with a battery installed, the Teridian production test programs the following six-byte sequence into the flash location starting at ...
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Data Sheet 71M6531D/F-71M6532D/F can voluntarily enter LCD or SLEEP modes. When system power is restored, the part will automatically transition from any of the battery modes to MISSION mode, once the PLL has settled. The MPU will run at 7/8 ...
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FDS 6531/6532 005 System Power (V3P3SYS) V1_OK Battery Current BROWNOUT MPU Mode WAKE MPU Clock Source PLL_OK Figure 22: Transition from BROWNOUT to MISSION Mode when System Power Returns V3P3SYS and VBAT V1_OK Battery Current MPU Mode MPU Clock Source ...
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Data Sheet 71M6531D/F-71M6532D/F VBAT Battery Current MPU Mode MPU Clock Source WAKE PLL_OK Internal RESETZ VBAT_OK Figure 24: Power-Up Timing with VBAT only 2.4 Fault and Reset Behavior 2.4.1 Reset Mode When the RESET pin is pulled high, all digital ...
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FDS 6531/6532 005 2.5 Wake-Up Behavior As described above, the part will always wake up in MISSION mode when system power is restored. Additionally, the part will wake up in BROWNOUT mode when PB rises (push button is pressed) or ...
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Data Sheet 71M6531D/F-71M6532D/F Samples 2.7 CE/MPU Communication Figure 27 shows the functional relationships between the CE and the MPU. The CE is controlled by the MPU via shared registers in the I/O RAM and in RAM. The CE outputs two ...
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FDS 6531/6532 005 3 Application Information 3.1 Connection of Sensors Figure 28 through Figure 30 show how resistive dividers, current transformers, Rogowski coils and resistive shunts are connected to the voltage and current inputs of the 71M6531. The analog input ...
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... For example, at +25°C, the expected error would be ±3° PPM/°C, or just 0.012%. The maximum deviation of ±2520 PPM (or 0.252%) is reached at the temperature extremes. If the refer- ence voltage is used to measure both voltage and current, the identical errors of ±0.252% add maximum Wh registration error of ± ...
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FDS 6531/6532 005 Error Band (PPM) over Temperature (°C) 2800 2400 2000 1600 1200 800 400 0 -400 -800 -1200 -1600 -2000 -2400 -2800 -40 -20 Figure 31: Error Band for VREF over Temperature 3.4.2 Temperature Compensation for VREF The ...
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Data Sheet 71M6531D/F-71M6532D/F 3.5 Connecting LCDs The 71M6531D/F and 71M6532D/F have an on-chip LCD controller capable of controlling static or multiplexed LCDs. Figure 32 shows the basic connection for an LCD. The following dedicated and multi-use pins can be assigned ...
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FDS 6531/6532 005 3.7 Connecting Three-Wire EEPROMs µWire EEPROMs and other compatible devices should be connected to the DIO pins DIO4 and DIO5, as shown in Figure 34 and described below: • DIO5 connects to both the DI and DO ...
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Data Sheet 71M6531D/F-71M6532D/F The polarity of the OPT_TX and OPT_RX pins can be inverted with the configuration bits, OPT_TXINV and OPT_RXINV, respectively. The OPT_TX output may be modulated at 38 kHz when system power is present. Modulation is not available ...
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FDS 6531/6532 005 3.11 Connecting the Reset Pin Even though a functional meter will not necessarily need a reset switch useful to have a reset push- button for prototyping as shown in (functional in MISSION mode only), V3P3D ...
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... The oscillator drives a standard 32.768 kHz watch crystal. The oscillator has been designed specifically to handle these crystals and is compatible with their high impedance and limited power handling capability. The oscillator power dissipation is very low to maximize the lifetime of any battery backup device attached to VBAT. ...
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FDS 6531/6532 005 3.17 Meter Calibration Once the Teridian 71M6531D/F or 71M6532D/F energy meter device has been installed in a meter system, it must be calibrated. A complete calibration includes the following: • Calibration of the metrology section, i.e. calibration ...
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Data Sheet 71M6531D/F-71M6532D/F 4 Firmware Interface 4.1 I/O RAM and SFR Map – Functional Order In Table 54, unimplemented (U) and reserved (R) bits are shaded in light gray. Unimplemented bits have no memory storage, writing them has no effect, ...
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FDS 6531/6532 005 Name Addr Bit 7 Digital I/O: 20AF 2008 DIO0 DIO_EEX[1:0] 2009 U DIO1 DIO2 200A U DIO3 200B U DIO4 200C U DIO5 200D U 200E U DIO6 200F R(0) DIO7 SFR 80 DIO8 SFR A2 SFR ...
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Data Sheet 71M6531D/F-71M6532D/F Name Addr Bit 7 LCD Display Interface: 2020 MUX_SYNC_E LCDX 2021 U LCDY LCD_MAP0 2023 LCD_BITMAP LCD_BITMAP LCD_MAP1 2024 [39]‡ 2025 LCD_MAP2 LCD_MAP3 2026 LCD_BITMAP LCD_BITMAP 2027 LCD_MAP4 [63] LCD_BITMAP LCD_BITMAP LCD_MAP5 2028 [71]‡ 2029 LCD_MAP6 LCD0 ...
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FDS 6531/6532 005 Name Addr Bit 7 LCD27 204B LCD28 204C LCD29 204D 204E LCD30 … … LCD33 2053 LCD36 2054 LCD37 2055 LCD38 2056 … … 2059 LCD41 LCD_BLNK 205A RTM: RTM0H 2060 2061 RTM0L 2062 RTM1H RTM1L 2063 ...
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Data Sheet 71M6531D/F-71M6532D/F Name Addr Bit 7 SLOT5 2096 SLOT6 2097 2098 SLOT7 2099 SLOT8 SLOT9 209A SPI Interrupt: 20B0 SPI0 20B1 SPI1 General-Purpose Nonvolatile Registers: GP0 20C0 … … 20C7 GP7 VERSION 20C8 Serial EEPROM: SFR 9E EEDATA SFR ...
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FDS 6531/6532 005 4.2 I/O RAM Description – Alphabetical Order The following conventions apply to the descriptions in this table: • Bits with a W (write) direction are written by the MPU into configuration RAM. Typically, they are initially stored ...
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Data Sheet 71M6531D/F-71M6532D/F Name Location Reset Wake COMP_STAT[0] 2003[0] – 2009[2:0] 0 DI_RPB[2:0] DIO_R1[2:0] 2009[6:4] 0 DIO_R2[2:0] 200A[2:0] 0 DIO_R4[2:0] 200B[2:0] 0 DIO_R5[2:0] 200B[6:4] 0 DIO_R6[2:0] 200C[2:0] 0 DIO_R7[2:0] 200C[6:4] 0 DIO_R8[2:0] 200D[2:0] 0 DIO_R9[2:0] 200D[6:4] 0 DIO_R10[2:0] 200E[2:0] 0 ...
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FDS 6531/6532 005 Name Location Reset Wake DIO_PV 2008[2] 0 DIO_PW 2008[3] 0 DIO_PX 200F[3] 0 DIO_PY 200F[2] 0 SFR 9E 0 EEDATA[7:0] SFR 9F 0 EECTRL[7:0] ECK_DIS 2005[5] 0 EQU[2:0] 2000[7:5] 0 EX_XFR 2002[0] 0 EX_RTC 2002[1] 0 EX_FWCOL ...
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Data Sheet 71M6531D/F-71M6532D/F Name Location Reset Wake FLSH_ERASE SFR 94[7:0] 0 [7:0] SFR B2[1] 0 FLSH_MEEN FLSH_PGADR SFR B7 [7:2] 0 [5:0] SFR B2[0] 0 FLSH_PWE 20C0 0 GP0 … … … 20C7 0 GP7 IE_FWCOL0 SFR E8[2] 0 IE_FWCOL1 ...
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FDS 6531/6532 005 Name Location Reset Wake IEN_WD_NROVF 20B0[0] 0 SFR E8[0] 0 IE_XFER IE_RTC SFR E8[1] 0 IE_WAKE SFR E8[5] 0 – INTBITS SFR F8[6:0] 2023 0 LCD_BITMAP [31:24] 2024 0 LCD_BITMAP [39:32] 2026 0 LCD_BITMAP [55:48] LCD_BITMAP 2027 ...
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Data Sheet 71M6531D/F-71M6532D/F Name Location Reset Wake LCD_DAC[2:0] 20AB[3:1] 0 LCD_E 2021[5] 0 LCD_MODE[2:0] 2021[4:2] 0 LCD_ONLY 20A9[5] 0 2030[3:0] 0 LCD_SEG0[3:0] … … … 2043[3:0] 0 LCD_SEG19[3:0] LCD_SEG24[3:0] 2048[3:0] 0 … … … LCD_SEG31[3:0] 204F[3:0] 0 LCD_SEG32[3:0] 2050[3:0] 0 ...
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FDS 6531/6532 005 Name Location Reset Wake LCD_SEG33[3:0] 2051[3:0] 0 … … … LCD_SEG35[3:0] 2053[3:0] 0 LCD_SEG37[3:0] 2055[3:0] 0 2057[3:0] 0 LCD_SEG39[3:0] … … … LCD_SEG41[3:0] 2059[3:0] 0 LCD_SEG48[7:4] 2036[7:4] 0 … … … LCD_SEG49[7:4] 2037[7:4] 0 LCD_SEG63[7:4] 2045[7:4] 0 ...
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... The modulation is applied after any inversion caused by OPT_TXINV Indicates that system power is present and the clock generation PLL is settled. Determines the maximum width of the pulse (low going pulse). The maximum pulse width is (2*PLS_MAXWIDTH + 1)*T FF R/W If PLS_INTERVAL = the sample time (397 µ ...
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FDS 6531/6532 005 Name Location Reset Wake 2004[6] 0 PLS_INV – SFRB2[7] PREBOOT 201C[2:0] 4 PREG[16:0] 201D[7:0] 0 201E[7:2] 0 PRE_SAMPS[1:0] 2001[7:6] 0 QREG[1:0] 201E[1:0] 0 RST_SUBSEC 2010[0] 0 RTCA_ADJ[6:0] 2011[6:0] 40 2015 RTC_SEC[5:0 * 2016 RTC_MIN[5:0] * 2017 RTC_HR[4:0] ...
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Data Sheet 71M6531D/F-71M6532D/F Name Location Reset Wake SFRB2[6] 0 SECURE 20AC[1] 0 SEL_IAN 20AC[5] 0 SEL_IBN SLEEP 20A9[6] 0 2090[3:0] 0 SLOT0_SEL[3:0] SLOT1_SEL[3:0] 2090[7:4] 1 SLOT2_SEL[3:0] 2091[3:0] 2 SLOT3_SEL[3:0] 2091[7:4] 3 SLOT0_ALTSEL 2096[3:0] A [3:0] SLOT1_ALTSEL 2096[7:4] 1 [3:0] 2097[3:0] ...
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... W disarmed whenever the MISSION or BROWNOUT mode. The timer must be armed at least three RTC cycles before the SLEEP or LCD-ONLY mode is commanded. – R/W Sleep time. Time = WAKE_PRD[2:0]*WAKE_RES. Default = 001. Maximum value is 7. – R/W Resolution of WAKE timer minute 2.5 seconds. 0 R/W This flag is set approximately 1 ms before the watchdog timer overflows cleared by writing the falling edge of WAKE ...
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Data Sheet 71M6531D/F-71M6532D/F 4.3 CE Interface Description 4.3.1 CE Program The CE performs the precision computations necessary to accurately measure energy. Different code variations are used for EQU[2: and EQU[2: The computations include offset ...
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FDS 6531/6532 005 • Select the values for SLOT0_SEL[3: SLOT1_SEL[3: SLOT2_SEL[3: SLOT3_SEL[3: • Select the values for SLOT0_ALTSEL[3:0] = 0x0A, SLOT1_ALTSEL[3: SLOT2_ALTSEL[3:0] = 0x0B, SLOT3_ALTSEL[3: • Set CHOP_E[1:0] ...
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Data Sheet 71M6531D/F-71M6532D/F Table 57: CESTATUS (CE RAM 0x80) Bit Definitions CESTATUS [bit] Name 31:29 Not Used Reserved 26 SAG_B 25 SAG_A 24:0 Not Used The CE is initialized and its functions are controlled by the MPU ...
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... When 0, enables the control of GAIN_ADJ by the CE. The number of consecutive voltage samples below SAG_THR 80 before a sag alarm is declared. The maximum value is 255. SAG_THR is at address 0x24. The combination of FREQSEL1 and FREQSEL0 selects the phase used for the frequency monitor, the phase-to-phase lag calculation, the zero-crossing counter MAINEDGE_X and the F0 bit (CESTATUS[28]) ...
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Data Sheet 71M6531D/F-71M6532D/F 4.3.7 CE Transfer Variables When the MPU receives the XFER_BUSY interrupt, it knows that fresh data is available in the transfer variables. CE transfer variables are modified during the CE code pass that ends with an XFER_BUSY ...
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... V and 30 A (3,600 W) results in one pulse per second. If the load is 240 V at 150 A (36,000 W), ten pulses per second will be generated. The maximum pulse rate is 7.5 kHz for APULSEW and APULSER and 1.2 kHz for APULSE2 and APULSE3. v1.3 © 2005-2010 TERIDIAN Semiconductor Corporation ...
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... Data Sheet 71M6531D/F-71M6532D/F The maximum time jitter is 67 µs and is independent of the number of pulses measured. Thus, if the pulse generator is monitored for one second, the peak jitter is 67 ppm. After 10 seconds, the peak jitter is 6.7 ppm. The average jitter is always zero attempted to drive either pulse generator faster than its maximum rate, it will simply output at its maximum rate without exhibiting any rollover characteristics ...
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FDS 6531/6532 005 CE Name Default Address 0 0x19 PHADJ_B 0 0x1F TEMP_NOM 9174 0x39 DEGSCALE 4.3.10 Other CE Parameters Table 66 shows the CE parameters used for suppression of noise due to scaling and truncation effects. The table also ...
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Data Sheet 71M6531D/F-71M6532D/F Figure 41: CE Data Flow: Multiplexer and ADC Figure 42: CE Data Flow: Scaling, Gain Control, Intermediate Variables 96 © 2005-2010 TERIDIAN Semiconductor Corporation FDS 6531/6532 005 v1.3 ...
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FDS 6531/6532 005 Figure 43: CE Data Flow: Squaring and Summation Stages v1.3 © 2005-2010 TERIDIAN Semiconductor Corporation Data Sheet 71M6531D/F-71M6532D/F 97 ...
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... These are stress ratings only and functional operation at these or any other conditions beyond those indicated under recommended operating conditions (Section 5.3) is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages are with respect to GNDA. ...
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FDS 6531/6532 005 5.2 Recommended External Components Table 68: Recommended External Components Name From To C1 V3P3A AGND C2 V3P3D GNDD CSYS V3P3SYS GNDD C2P5 V2P5 GNDD XTAL XIN XOUT CXS XIN AGND CXL XOUT AGND Notes: 1. AGND and ...
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Data Sheet 71M6531D/F-71M6532D/F 5.4 Performance Specifications 5.4.1 Input Logic Levels Parameter a Digital high-level input voltage a Digital low-level input voltage , V Input pull-up current E_RXTX, E_RST, CKTEST Other digital inputs Input pull down current ...
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... V3P3SYS current (CE on) CKMPU = 614 kHz No Flash Memory write V3P3A current RTM_E=0, ECK_DIS=1, VBAT current ADC_E=1, ICE_E=0 Normal Operation as above, except V3P3SYS current, write Flash at maximum rate, Write Flash CE_E = 0, ADC_ VBAT=3.6V VBAT current 5.4.6 V3P3D Switch Table 75: V3P3D Switch Performance Specifications Parameter On resistance – ...
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... VLC0 Voltage, ⅓ bias VLC1 Impedance VLC0 Impedance 1 VLCD is V3P3SYS in MISSION mode and VBAT in BROWNOUT and LCD modes. † Specified as percentage of VLC2, the maximum LCD voltage. 5.4.12 Optical Interface Table 81: Optical Interface Performance Specifications Parameter OPT_TX V (V3P3D-OPT_TX) OH OPT_TX V ...
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FDS 6531/6532 005 5.4.13 Temperature Sensor Table 82 shows the performance for the temperature sensor. The LSB values do not include the 8-bit left shift at CE input. Table 82: Temperature Sensor Performance Specifications Parameter Nominal relationship: N( ...
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Data Sheet 71M6531D/F-71M6532D/F Parameter VNOM temperature coefficients: TC1 TC2 VREF(T) deviation from VNOM(T) − 6 VREF ( T ) VNOM ( − VNOM ( T ) max VREF aging a This relationship describes the nominal ...
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FDS 6531/6532 005 5.5 Timing Specifications 5.5.1 Flash Memory Table 85: Flash Memory Timing Specifications Parameter Flash Read Pulse Width Flash write cycles Flash data retention Flash data retention Flash byte write operations between page or mass erase operations Write ...
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Data Sheet 71M6531D/F-71M6532D/F 5.5.5 SPI Slave Port (MISSION Mode) Table 88: SPI Slave Port (MISSION Mode) Timing Parameter t PCLK cycle time SPIcyc t Enable lead time SPILead t Enable lag time SPILag t PCLK pulse width: SPIW High Low ...
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FDS 6531/6532 005 5.6 Typical Performance Data 5.6.1 Accuracy over Current Figure 45 shows accuracy over current for various load angles at room temperature. 1 0.75 0.5 0.25 0 -0.25 -0.5 -0.75 -1 0.1 1 Figure 45: Wh Accuracy, 0.1 ...
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Data Sheet 71M6531D/F-71M6532D/F 5.7 71M6531D/F Package 5.7.1 Package Outline PIN #1 DOT MARKING 0.850 ±0.050 Figure 46: QFN-68 Package Outline, Top and Side View 0.400 ±0.050 0.200 ±0.050 PIN #1 ID R0.20, or CHAMFER 0.500 x 45° Figure 47: QFN-68 ...
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... SEG3/PCLK 7 V3P3D 8 SEG19/CKTEST 9 V3P3SYS 10 SEG4/PSDO 11 SEG5/PCSZ 12 SEG37/DIO17 13 COM0 14 COM1 15 COM2 16 COM3 17 v1.3 © 2005-2010 TERIDIAN Semiconductor Corporation TERIDIAN 71M6531D-IM 71M6531F-IM Figure 48: Pinout for QFN-68 Package Data Sheet 71M6531D/F-71M6532D/F RESET 51 V2P5 50 VBAT SEG48/DIO28 47 SEG31/DIO11 46 SEG30/DIO10 45 SEG29/DIO9/YPULSE 44 SEG28/DIO8/XPULSE 43 SEG27/DIO7/RPULSE 42 SEG26/DIO6/WPULSE 41 SEG25/DIO5/SDATA 40 SEG24/DIO4/SDCK ...
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Data Sheet 71M6531D/F-71M6532D/F 5.7.3 Recommended PCB Land Pattern for the QFN-68 Package Figure 49: PCB Land Pattern for QFN 68 Package Table 89: Recommended PCB Land Pattern Dimensions Symbol Notes not place ...
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FDS 6531/6532 005 5.8 71M6532D/F Package 5.8.1 71M6532D/F Pinout (LQFP-100) GNDD 1 SEG9/E_RXTX 2 DIO2/OPT_TX 3 TMUXOUT SEG3/PCLK 6 V3P3D 7 SEG19/CKTEST 8 V3P3SYS 9 SEG4/PSDO 10 SEG5/PCSZ 11 SEG37/DIO17 12 SEG38/DIO18/MTX 13 DIO56 14 DIO57 15 ...
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Data Sheet 71M6531D/F-71M6532D/F 5.8.2 LQFP-100 Mechanical Drawing 1 14.000 +/- 0.200 0.225 +/- 0.045 Figure 51: LQFP-100 Package, Mechanical Drawing 112 © 2005-2010 TERIDIAN Semiconductor Corporation 15.7(0.618) 16.3(0.641) Top View MAX. 1.600 1.50 +/- 0.10 0.50 TYP. 0.10 +/- 0.10 ...
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FDS 6531/6532 005 5.9 Pin Descriptions Pin types Power Output Input, I/O = Input/Output The circuit number denotes the equivalent circuit, as specified under Section 5.9.1 Power and Ground Pins Name Type Circuit Analog ...
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Data Sheet 71M6531D/F-71M6532D/F 5.9.3 Digital Pins Name Type Circuit COM3,COM2 COM1,COM0 SEG0…SEG2, SEG7, SEG8 O 5 SEG12…SEG18 SEG20…SEG23 O 5 SEG24/DIO4… SEG35/DIO15, SEG37/DIO17, SEG48/DIO28, I SEG49/DIO29, SEG63/DIO43… SEG66/DIO46 SEG3/PCLK SEG4/PSDO I Multi-use ...
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FDS 6531/6532 005 5.9.4 I/O Equivalent Circuits V3P3D V3P3D 110K Digital CMOS Input Input Pin GNDD Digital Input Equivalent Circuit Type 1: Standard Digital Input or pin configured as DIO Input with Internal Pull-Up V3P3D Digital CMOS Input Input Pin ...
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... Tape and reel 71M6531D-IMR/F 256 KB Bulk 71M6531F-IM/F 256 KB Tape and reel 71M6531F-IMR/F 128 KB Bulk 71M6532D-IGT/F 128 KB Tape and reel 71M6532D-IGTR/F 256 KB Bulk 71M6532F-IGT/F 256 KB Tape and reel 71M6532F-IGTR/F FDS 6531/6532 005 Package Mark- ing 71M6531D-IM 71M6531D-IM 71M6531F-IM 71M6531F-IM 71M6532D-IGT 71M6532D-IGT 71M6532F-IGT 71M6532F-IGT v1.3 ...
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FDS 6531/6532 005 Appendix A: Acronyms AFE Analog Front End AMR Automatic Meter Reading ANSI American National Standards Institute CE Compute Engine DIO Digital I /O DSP Digital Signal Processor FIR Finite Impulse Response Inter-IC Bus ICE ...
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Data Sheet 71M6531D/F-71M6532D/F Appendix B: Revision History Revision Date 1.3 June 9, 2010 118 © 2005-2010 TERIDIAN Semiconductor Corporation Description 1) Throughout document: Added bit ranges to all register fields where missing (e.g. MPU_DIV[2:0]). 2) Figure 1, Figure 2: corrected ...
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... Figure 46 to 0.1 mm. Corrected bit range for CE_LCTN to [7:0] and functional description for TMOD[7] and TMOD[3] in Table 22. Added maximum value for WRATE and text stating that registers RTC_SEC to RTC_YR do not change at reset. Added V LSB entry for sag detection in CE Interface Description, text regarding hysteresis at section 3 ...
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Data Sheet 71M6531D/F-71M6532D/F © 2008-2010 Teridian Semiconductor Corporation. All rights Reserved. Teridian Semiconductor Corporation is a registered trademark of Teridian Semiconductor Corporation. Single Converter Technology is a registered trademark of Teridian Semiconductor Corporation. Simplifying System Integration is a trademark of ...