71M6533 Maxim, 71M6533 Datasheet - Page 129

• Manufacturer Part Number: 71M6533
• Description: The Teridian™ 71M6533 and 71M6534 are third-generation polyphase metering systems-on-chips (SoCs) with a 10MHz 8051-compatible MPU core, low-power RTC, flash, and LCD driver
• Manufacturer: Maxim

Appendix B: Revision History
Rev 2
REVISION
NUMBER
1.2
2
August 3, 2010
REVISION
DATE
2/12
1) Throughout document: Added bit ranges to all register fields where
2)
3) Section
4) Section 1.1.1,
5) Clarified Section
6) Section
10) Section
11) Section
7) Section
8) (page 39) Section
9) (page
1) Added Guaranteed By Design notes to the Electrical Specifications.
2) Added explanation on NV properties of RTCA_ADJ[ ] and
3) Added note that transitions to BROWNOUT mode must be avoided
4) Added note in Application Section (3.1) stating that filter com-
5) Consolidated spelling of low-power modes (SLEEP, LCD,
6) Corrected value for C2 capacitor in Table 68.
7) Extended explanation of WD_OVF (not preserved in SLEEP mode)
8) Added explanation of WD_NROVF_FLAG.
9) Added explanation on MPU activity on transition to BROWNOUT
missing (e.g. MPU_DIV[2:0]).
Figure
for ADC resolution.
Added note – not all CE codes support all equations.
current in or out of DIO pins. Updated
 (page 19)
 (page 19): Changed providing Library to providing demonstration
 (page 20) Added note about MUX_DIV=0 disables ADC output.
 (page 21) See restrictions on INTBITS register.
 (page 22) Added P1-P3 to
 (page 24) Updated Data Pointer description.
 (page 25)
 (page 26) Section 1.4.6: Clarified SOBUF, S1BUF as Tx and Rx
 (page 27): Added caution on proper way to clear flag bits.
 (page
 (page 37)
 (page 38): Added caution concerning frequency relationship to
for observing RTC timing on TMUXOUT pin.
PREG/QREG[ ] and corrected entries in Table 54.
during page erase operations.
ponents other that those shown on the Demo Boards should not be
connected to the sensor input pins. Added reference to AN5292.
BROWNOUT) and of COMPSTAT register.
mode in section 2.4.2.
and corrected entries in Table 54.
I/O RAM access via the SPI interface. Added
frequencies.
source code.
and WRPROT_BT bits. Updated description for FWCOL0,
FWCOL1.
buffers.
specific CE code.
46)
1: Corrected name for PSDI and PSDO signals.
1.5.2 PLL and Internal Clocks
1.2.3
1.4 80515 MPU Core:
31) Table
2.3 Battery Modes
1.5.11 SPI Slave
Section
Table
Table 14:
Table
(page
Table 5
1.3.2
1.5.7 Digital
25: Added Interrupt sources for Ext. Interrupts 2-6.
1.5.3 Real-Time Clock
6: Change approximate frequencies to exact
37: Changed frequencies to exact frequencies.
11):
(page 15): Corrected equations for EQU=3.
Added note about clearing the WRPROT_CE
(page 16).
Added note concerning tailoring CE code
DESCRIPTION
Port, (page 52): Clarified description of
(page 57): Added details on software
Table 10.
I/O: Added caution about not sourcing
Figure
(RTC): Added description
9.
Table
48.
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