73S8024RN Maxim, 73S8024RN Datasheet - Page 10

• Manufacturer Part Number: 73S8024RN
• Description: The 73S8024RN is a single smart card interface IC, compliant to the electrical requirements of ISO 7816-3, EMV 4
• Manufacturer: Maxim

73S8024RN Data Sheet
7 Activation Sequence
The 73S8024RN smart card interface IC has an internal 10ms delay at power on reset or on the
application of V
be set low to activate the card. In order to initiate activation, the card must be present; there can be no
over-temperature fault or no V
The following steps show the activation sequence and the timing of the card control signals when the
system controller sets CMDVCC low while the RSTIN is low:
•
•
•
•
•
10
CMDVCC is set low.
Next, the internal V
the voltage V
to report a fault to the system controller, and the power V
Turn I/O (AUX1, AUX2) to reception mode at the end of (t
CLK is applied to the card at the end of (t
RST is a copy of RSTIN after (t
set RST high until 42000 clock cycles after the start of CLK.
CMDVCC
RSTIN
VCC
RST
CLK
I/O
Figure 2: Activation Sequence – RSTIN Low When CMDVCC Goes Low
DD
t
t
t
t
1
2
3
4
CC
> V
= 0.510 ms (timing by 1.5MHz internal Oscillator)
= 1.5µs, I/O goes to reception state
= >0.5µs, CLK starts
≥
to the card becomes valid during t
42000 card clock cycles. Time for RST to become the copy of RSTIN
DDF
CC
. No activation is allowed at this time. The CMDVCC (edge triggered) must then
control circuit checks the presence of V
DD
fault.
4
). RSTIN may be set high before t
t
1
3
).
t
2
1
. If V
CC
t
CC
3
2
).
does not become valid, the OFF goes low
to the card is shut off.
CC
at the end of t
4
, however the sequencer will not
t
4
1
. In normal operation,
DS_8024RN_020
Rev. 1.9