DS4510 Maxim, DS4510 Datasheet - Page 7

• Manufacturer Part Number: DS4510
• Description: The DS4510 is a CPU supervisor with integrated 64-byte EEPROM memory and four programmable, nonvolatile (NV) I/O pins
• Manufacturer: Maxim

transistors. Read the I/O status register (F8h) to deter-
mine the logic levels present at the I/O pins.
Three types of memory are present in the DS4510
(EEPROM, SEEPROM, and SRAM). The main user
memory is 64 bytes of EEPROM starting at address
00h. This memory is not SRAM shadowed, so all writes
to these locations result in EEPROM write cycles
regardless of the state of the SEE bit. Additional memo-
ry for storing application data includes 6 bytes of SRAM
(FAh–FFh), and 2 bytes of SEEPROM (F2h, F3h). Refer
to the register memory map
addresses and memory types. Figure 4 shows the bit
names for the memory-mapped I/O bytes and their fac-
tory default values.
The higher-order bits of the I/O registers that are not
used, such as the four most significant bits of the
pullup-enable byte (address F0h), can be used as
additional memory. It is the responsibility of the appli-
cation to ensure that writes to these bytes do not
adversely affect bits controlling special functions of the
DS4510.
Figure 3. Register Memory Map
00
USER BYTE
08
USER BYTE
10
USER BYTE
18
USER BYTE
20
USER BYTE
28
USER BYTE
30
USER BYTE
38
USER BYTE
40
E8
F0
PULLUP ENABLE
F8
I/O STATUS
*ITALICIZED BYTES HAVE BIT DESCRPTIONS, REFER TO FIGURE 3.
CPU Supervisor with Nonvolatile Memory and
SRAM
SEE
EE
EE
EE
EE
EE
EE
EE
EE
01
USER BYTE
09
USER BYTE
11
USER BYTE
19
USER BYTE
21
USER BYTE
29
USER BYTE
31
USER BYTE
39
USER BYTE
41
E9
F1
RESET DELAY
F9
CONFIG
SRAM
SEE
EE
EE
EE
EE
EE
EE
EE
EE
02
User byte
0A
USER BYTE
12
USER BYTE
1A
USER BYTE
22
USER BYTE
2A
USER BYTE
32
USER BYTE
3A
USER BYTE
42
EA
F2
USER BYTE
FA
USER BYTE
(Figure
_____________________________________________________________________
User Memory
SRAM
3) for register
SEE
EE
EE
EE
EE
EE
EE
EE
EE
03
USER BYTE
0B
USER BYTE
13
USER BYTE
1B
USER BYTE
23
USER BYTE
2B
USER BYTE
33
USER BYTE
3B
USER BYTE
43
EB
F3
USER BYTE
FB
USER BYTE
SRAM
RESERVED
SEE
EE
EE
EE
EE
EE
EE
EE
EE
04
USER BYTE
0C
USER BYTE
14
USER BYTE
1C
USER BYTE
24
USER BYTE
2C
USER BYTE
34
USER BYTE
3C
USER BYTE
44
EC
F4
I/O
FC
USER BYTE
3
Figure 1. CPU Supervisor Power-Up and Power-Down Timing
Figure 2. How to Read the Memory Map
CONTROL
V
CCTP (MIN)
SRAM
SEE
EE
EE
EE
EE
EE
EE
EE
EE
REGISTER ADDRESS (HEX)
05
USER BYTE
0D
USER BYTE
15
USER BYTE
1D
USER BYTE
25
USER BYTE
2D
USER BYTE
35
USER BYTE
3D
USER BYTE
45
ED
F5
I/O
FD
USER BYTE
Programmable I/O
2
V
CONTROL
CCTP
t
V
RPU
CCTP (MAX)
t
R
V
OH
SRAM
F8
I/O STATUS
SEE
EE
EE
EE
EE
EE
EE
EE
EE
REGISTER NAME
06
USER BYTE
0E
USER BYTE
16
USER BYTE
1E
USER BYTE
26
USER BYTE
2E
USER BYTE
36
USER BYTE
3E
USER BYTE
46
EE
F6
I/O
FE
USER BYTE
1
CONTROL
SRAM
V
CCTP (MAX)
SRAM
SEE
MEMORY TYPE
EE
EE
EE
EE
EE
EE
EE
EE
V
CCTP
07
USER BYTE
0F
USER BYTE
17
USER BYTE
1F
USER BYTE
27
USER BYTE
2F
USER BYTE
37
USER BYTE
3F
USER BYTE
47
EF
F7
I/O
FF
USER BYTE
0
CONTROL
t
RPD
V
CCTP (MIN)
V
OL
t
F
SRAM
SEE
EE
EE
EE
EE
EE
EE
EE
EE
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