MAX7328 Maxim, MAX7328 Datasheet - Page 7

• Manufacturer Part Number: MAX7328
• Description: The MAX7328/MAX7329 are 2-wire serial-interfaced peripherals with eight I/O ports
• Manufacturer: Maxim

typically 4.7kΩ, is required on SDA. The MAX7328 or
MAX7329 SCL line operates only as an input. A pullup
resistor, typically 4.7kΩ, is required on SCL if there are
multiple masters on the 2-wire interface, or if the master
in a single-master system has an open-drain SCL output.
Figure 7. Slave Address
Figure 4. START and STOP Conditions
Figure 5. Bit Transfer
Figure 6. Acknowledge
TRANSMITTER
SDA
SCL
SDA
SCL
SDA
SCL
RECEIVER
CONDITION
SDA BY
SDA BY
START
SCL
S
CONDITION
START
DATA LINE STABLE;
MSB
S
A6
DATA VALID
_______________________________________________________________________________________
1
I
2
CHANGE OF DATA
A5
ALLOWED
C Port Expanders with Eight I/O Ports
2
FOR ACKNOWLEDGEMENT
A4
CLOCK PULSE
8
A3
CONDITION
STOP
9
P
A2
Each transmission consists of a START condition
(Figure 4) sent by a master, followed by the MAX7328
or MAX7329 7-bit slave address plus R/W bit, a register
address byte, one or more data bytes, and finally a
STOP condition (Figure 4).
Both SCL and SDA remain high when the interface is
not busy. A master signals the beginning of a transmis-
sion with a START (S) condition by transitioning SDA
from high to low while SCL is high. When the master
has finished communicating with the slave, it issues a
STOP (P) condition by transitioning SDA from low to
high while SCL is high. The bus is then free for another
transmission (Figure 4).
One data bit is transferred during each clock pulse.
The data on SDA must remain stable while SCL is high
(Figure 5).
The acknowledge bit is a clocked ninth bit, which the
recipient uses to handshake receipt of each byte of
data (Figure 6). Thus, each byte transferred effectively
requires 9 bits. The master generates the ninth clock
pulse, and the recipient pulls down SDA during the
acknowledge clock pulse, so the SDA line is stable low
during the high period of the clock pulse. When the
master is transmitting to the MAX7328 or MAX7329, the
MAX7328 or MAX7329 generates the acknowledge bit
because the MAX7328 or MAX7329 is the recipient.
When the MAX7328 or MAX7329 is transmitting to the
master, the master generates the acknowledge bit
because the master is the recipient.
The MAX7328/MAX7329 have a 7-bit long slave
address (Figure 7). The eighth bit, following the 7-bit
slave address, is the R/W bit. It is low for a write com-
mand, high for a read command.
A1
START and STOP Conditions
LSB
A0
R/W
Slave Address
Acknowledge
Bit Transfer
ACK
7