DS34RT5110SQE/NOPB National Semiconductor, DS34RT5110SQE/NOPB Datasheet
DS34RT5110SQE/NOPB
Specifications of DS34RT5110SQE/NOPB
Related parts for DS34RT5110SQE/NOPB
DS34RT5110SQE/NOPB Summary of contents
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... The transmitter supports configurable transmit de-emphasis so the output can be optimized for driving additional lengths of cables or FR4 traces. Application Diagram © 2010 National Semiconductor Corporation DS34RT5110 Features ■ Optimized for HDMI/DVI repeater applications ■ ...
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Pin Descriptions Pin Name Pin Number I/O, Type High Speed Differential I/O C_IN− CML C_IN+ 2 D_IN0− CML D_IN0+ 5 D_IN1− CML D_IN1+ 9 D_IN2− CML D_IN2+ 12 C_OUT CML ...
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Pin Name Pin Number I/O, Type Power Power DD 10, 13, 15, 46 GND 22, 24, GND 27, 30, 31, 34 Exposed DAP GND DAP Other Reserv 16, 17, 18, 19, 20, 23 Note ...
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... Absolute Maximum Ratings If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage ( LVCMOS Input Voltage LVCMOS Output Voltage CML Input/Output Voltage Junction Temperature Storage Temperature Lead Temp. (Soldering, 5 sec.) Electrical Characteristics Over recommended operating supply and temperature ranges unless otherwise specified ...
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Symbol Parameter Condition CML Inputs Input Voltage Measured differentially at VTX Swing (Launch TPA, Figure 1, note 4 Amplitude) DC-Coupled requirement Input Common- Measured at TPB, VICMDC Mode Voltage VINmin = 800mV, VINmax = 1200mV, Measured differentially at Input Voltage ...
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Symbol Parameter Condition Data Channel Random Jitter RJ Random Jitter (Note Data Channel CDR Jitter Generation Data Paths, measured at Total Output Jitter TPC PRBS7, EQ [2:0] = 000 TROJ1 0.25 Gbps Figure Note Data Paths, measured at Total Output ...
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Setup and Timing Diagrams FIGURE 2. CML Output Swings at A/B (VOD_CRL = 24 kΩ) FIGURE 1. Test Setup Diagram 7 30087310 30087312 www.national.com ...
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FIGURE 3. CML Output Transition Times FIGURE 4. CML Latency Delay Time FIGURE 5. SD – LOCK Delay Time 8 30087311 30087313 30087314 ...
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Functional Description The DS34RT5110 DVI, HDMI Retimer with Input Equalization and Output De-Emphasis consists of three data channels and PHASE-LOCKED-LOCKED LOOP (PLL) The clock channel has a high-performance PLL that creates a low jitter sampling clock for the clock and ...
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OUTPUT VO CONTROL Output differential voltage (VO) is controlled through VOD_CRL pin ties an external resistor to the ground as shown EQ2 INPUTS DE1 External Resistor Value (VOD_CRL ...
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RETIMING AND DE-EMPHASIS BYPASS The retiming and De-emphasis BYPASS pin provides the flexibility to configure the device to an equalizer only mode. The device is in normal operation, when holding a LOW state on the BYPASS pin. The retiming and ...
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Application Information The DS34RT5110 is a DVI/HDMI video signal reconditioning device. The device conforms to DVI v1.0 and HDMI v1.3a standards supporting up to 10.2 Gbps total throughput TMDS data for 1080p with 48 bit deep color depth. TYPICAL APPLICATION ...
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MATRIX SWITCH APPLICATION For the security system with matrix DVI/HDMI switches, the DS34RT5110 is ideal to equalize the long cable reach re- DUAL LINK APPLICATION The DS34RT5110 supports DVI dual link applications requir- ing ultra-high resolutions for QXGA and WQXGA. ...
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CABLE SELECTION AND INTER-PAIR SKEW DVI v1.0 and HDMI v1.3a specify Inter-Pair Skew require- ments for the system. The DS34RT5110 intends to extend the longer cable reach with STP (DVI / HDMI) cable, or UTP (Cat5 / Cat5e / Cat6) ...
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General Recommendations The DS34RT5110 is a high performance circuit capable of delivering excellent performance. To achieve optimal perfor- mance, careful attention must be paid to the details associ- ated with high-speed design as well as providing a clean power supply. ...
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Typical Performance Characteristics as a Repeater FIGURE 16. Simplified Test Setup as a Single Repeater FIGURE 17. System Source Eye Diagram at TPA (3.4 Gbps) FIGURE 19. Device Source Eye Diagram at TPC (3.4 Gbps, Cable A = 20m 28 ...
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FIGURE 22. System Source Eye Diagram at TPA (2.25 Gbps) FIGURE 24. Device Source Eye Diagram at TPC (2.25 Gbps, Cable A = 25m 28 AWG HDMI 0x05, BYPASS = 0dB) FIGURE 26. System Sink ...
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FIGURE 27. System Source Eye Diagram at TPA (1.65 Gbps) FIGURE 29. Device Source Eye Diagram at TPC (1.65 Gbps, Cable A = 35m 28 AWG HDMI 0x05, BYPASS = 0dB) FIGURE 31. System Sink ...
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Physical Dimensions inches (millimeters) unless otherwise noted 7mm x 7mm 48-pin LLP Package Order Number DS34RT5110SQ Package Number SQA48A 19 www.national.com ...
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... For more National Semiconductor product information and proven design tools, visit the following Web sites at: www.national.com Products Amplifiers www.national.com/amplifiers Audio www.national.com/audio Clock and Timing www.national.com/timing Data Converters www.national.com/adc Interface www.national.com/interface LVDS www.national.com/lvds Power Management www.national.com/power Switching Regulators www.national.com/switchers LDOs www.national.com/ldo LED Lighting www ...