MAX3580ETJ+ Maxim Integrated Products, MAX3580ETJ+ Datasheet - Page 16

• Manufacturer Part Number: MAX3580ETJ+
• Description: IC TUNER TV DIRECT CONV 32TQFN
• Manufacturer: Maxim Integrated Products
• Type: Direct Conversion TV Tunerr

Specifications of MAX3580ETJ+

• Applications: Set-Top Boxes
• Mounting Type: Surface Mount
• Package / Case: 32-TQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Direct-Conversion TV Tuner
IMPORTANT NOTICE: When reading other addresses
than 8’h00 (the system trim bits), it is possible that the
data going to the bias cells will be disturbed due to the
architecture of the fuse bank. This means the bias cur-
rent could change while reading back fuse data.
1) Write 8’hXX to TFA. XX is the address of the fuse col-
2) Read 8’hXX from TFR. TFR is the Tracking Filter
3) Repeat steps 1 and 2 for other addresses.
The MAX3580 uses a 2-wire I
face consisting of a serial-data line (SDA) and a serial-
clock line (SCL). The serial interface allows
communication between the MAX3580 and the master
at clock frequencies up to 400kHz. The master initiates
a data transfer on the bus and generates the SCL sig-
nal to permit data transfer. The MAX3580 behaves as
slave devices that transfer and receive data to and from
the master. Pull SDA and SCL high with external pullup
resistors (1kΩ or greater) for proper bus operation.
One bit is transferred during each SCL clock cycle. A
minimum of nine clock cycles are required to transfer a
byte in or out of the MAX3580 (8 bits and an ACK/NACK).
The data on SDA must remain stable during the high peri-
od of the SCL clock pulse. Changes in SDA while SCL is
high and stable are considered control signals (see the
START and STOP Conditions section). Both SDA and
SCL remain high when the bus is not busy.
The master initiates a transmission with a START condi-
tion (S), which is a high-to-low transition on SDA while
SCL is high. The master terminates a transmission with
a STOP condition (P), which is a low-to-high transition
on SDA while SCL is high.
Figure 2. MAX3580 Slave Address Byte
16
umn you want to read.
Read Register.
SDA
SCL
______________________________________________________________________________________
S
1
1
START and STOP Conditions
2-Wire Serial Interface
2
C-compatible serial inter-
To Read Back Fuses
1
2
3
0
SLAVE ADDRESS
0
4
Data transfers are framed with an acknowledge bit
(ACK) or a not-acknowledge bit (NACK). Both the mas-
ter and the MAX3580 (slave) generate acknowledge
bits. To generate an acknowledge, the receiving device
must pull SDA low before the rising edge of the
acknowledge-related clock pulse (ninth pulse) and
keep it low during the high period of the clock pulse.
To generate a not-acknowledge condition, the receiver
allows SDA to be pulled high before the rising edge of
the acknowledge-related clock pulse, and leaves SDA
high during the high period of the clock pulse.
Monitoring the acknowledge bits allows for detection of
unsuccessful data transfers. An unsuccessful data
transfer happens if a receiving device is busy or if a
system fault has occurred. In the event of an unsuc-
cessful data transfer, the bus master must reattempt
communication at a later time.
The MAX3580 has a 7-bit slave address that must be
sent to the device following a START condition to initi-
ate communication. The slave address is determined
by the state of the ADDR2 pin and is equal to
11000[ADDR2]0 (see Table 4). The eighth bit (R/W) fol-
lowing the 7-bit address determines whether a read or
write operation will occur.
The MAX3580 continuously awaits a START condition
followed by its slave address. When the device recog-
nizes its slave address, it acknowledges by pulling the
SDA line low for one clock period; it is ready to accept
or send data depending on the R/W bit (Figure 2).
Table 4. Address Configuration
0
5
ADDRESS (WRITE/READ)
Acknowledge and Not-Acknowledge Conditions
ADDR2
C4/C5
C0/C1
6
HEX
HEX
7
0
R/ W
8
ACK
ADDR2
9
Slave Address
0
1