MAX44007 Maxim, MAX44007 Datasheet - Page 16

• Manufacturer Part Number: MAX44007
• Description: The MAX44007 ambient light sensor features an I²C digital output that is ideal for a number of portable applications such as smartphones, notebooks, and industrial sensors
• Manufacturer: Maxim

Low-Power Digital Ambient Light Sensor
with Enhanced Sensitivity
Figure 3. 2-Wire Interface Timing Diagram
SMBus is a trademark of Intel Corp.
16
The IC features an I
serial interface consisting of a serial-data line (SDA) and
a serial-clock line (SCL). SDA and SCL facilitate com-
munication between the IC and the master at clock rates
up to 400kHz. Figure 3 shows the 2-wire interface timing
diagram. The master generates SCL and initiates data
transfer on the bus. A master device writes data to the
IC by transmitting the proper slave address followed by
the register address and then the data word. Each trans-
mit sequence is framed by a START (S) or REPEATED
START (Sr) condition and a STOP (P) condition. Each
word transmitted to the IC is 8 bits long and is followed
by an acknowledge clock pulse. A master reading data
from the IC transmits the proper slave address followed
by a series of nine SCL pulses. The IC transmits data on
SDA in sync with the master-generated SCL pulses. The
master acknowledges receipt of each byte of data. Each
read sequence is framed by a START or REPEATED
START condition, a not acknowledge, and a STOP condi-
tion. SDA operates as both an input and an open-drain
output. A pullup resistor, typically greater than 500I, is
required on the SDA bus. SCL operates as only an input.
A pullup resistor, typically greater than 500I, is required
on SCL if there are multiple masters on the bus, or if the
master in a single-master system has an open-drain SCL
output. Series resistors in line with SDA and SCL are
optional. Series resistors protect the digital inputs of the
SDA
SCL
t HD,STA
CONDITION
START
t LOW
2
I
C/SMBus™-compatible, 2-wire
t R
2
C Serial Interface
t HIGH
t SU,DAT
t F
t HD,DAT
t SU,STA
START CONDITION
IC from high-voltage spikes on the bus lines, and mini-
mize crosstalk and undershoot of the bus signals.
One data bit is transferred during each SCL cycle. The
data on SDA must remain stable during the high period
of the SCL pulse. Changes in SDA while SCL is high are
control signals (see the START and STOP Conditions
section). SDA and SCL idle high when the I
busy.
SDA and SCL idle high when the bus is not in use. A
master initiates communication by issuing a START con-
dition. A START condition is a high-to-low transition on
SDA with SCL high. A STOP condition is a low-to-high
transition on SDA while SCL is high (Figure 4). A START
condition from the master signals the beginning of a
transmission to the IC. The master terminates transmis-
sion, and frees the bus, by issuing a STOP condition. The
bus remains active if a REPEATED START condition is
generated instead of a STOP condition.
The IC recognizes a STOP condition at any point during
data transmission except if the STOP condition occurs in
the same high pulse as a START condition. For proper
operation, do not send a STOP condition during the
same SCL high pulse as the START condition.
REPEATED
t HD,STA
START and STOP Conditions
t SP
Early STOP Conditions
t SU,STO
CONDITION
STOP
Bit Transfer
2
t BUF
C bus is not
CONDITION
START