MAX4356 Maxim, MAX4356 Datasheet - Page 11

• Manufacturer Part Number: MAX4356
• Description: The MAX4356 is a 16 x 16 highly integrated video crosspoint switch matrix with input and output buffers and On-Screen Display (OSD) Insertion
• Manufacturer: Maxim

SWITCHING CHARACTERISTICS
((V
V
noted. Typical values are at T
Note 1: Associated output voltage may be determined by multiplying the input voltage by the specified gain (A
Note 2: Logic-level characteristics apply to the following pins: DIN, DOUT, SCLK, CE, UPDATE, RESET, A3–A0, MODE, AOUT, and
Note 3: Switching transient settling time is guaranteed by the settling time (t
Note 4: Input test signal: 3.58MHz sine wave of amplitude 40IRE superimposed on a linear ramp (0 to 100IRE). IRE is a unit of
Note 5: All devices are 100% production tested at T
with On-Screen Display Insertion and I/O Buffers
OSDFILL
Delay: UPDATE to Video Out
Delay: UPDATE to AOUT
Delay: OSDKEY_ to Output
Delay: SCLK to DOUT Valid
Delay: Output Disable
Delay: Output Enable
Setup: CE to SCLK
Setup: DIN to SCLK
Hold Time: SCLK to DIN
Minimum High Time: SCLK
Minimum Low Time: SCLK
Minimum Low Time: UPDATE
Setup Time: UPDATE to SCLK
Hold Time: SCLK to UPDATE
Setup Time: MODE to SCLK
Hold Time: MODE to SCLK
Minimum Low Time: RESET
Delay: RESET
CC
- V
offset voltage. Gain is specified for IN_ and OSDFILL_ signal paths.
OSDKEY_.
ing the switch matrix.
video-signal amplitude developed by the International Radio Engineers: 140IRE = 1.0V.
_ = +1.75V for single supply, R
EE
16 x 16 Nonblocking Video Crosspoint Switch
PARAMETER
) = +4.5V to +10.5V, V
______________________________________________________________________________________
A
= +25°C. )
DD
SYMBOL
t
t
t
t
t
t
PdOkVo/
t
t
t
t
PdUdVo
PdUdAo
t
t
PdOfVo
HdHUd
t
MnLRst
t
PdHOe
MnHCk
MnLUd
SuHUd
t
t
PdLOe
t
MnLCk
t
t
HdMd
PdDo
SuMd
PdRst
SuCe
HdDi
SuDi
= +2.7V to +5.5V, DGND = AGND = 0, V
L
= 150
V
MODE = 0, time to AOUT = low after
UPDATE = low
V
V
Output disabled, 1k pulldown to AGND,
V
Rising edge of UPDATE to falling edge of
SCLK
Falling edge of SCLK to falling edge of
UPDATE
Minimum time from clock edge to MODE
with valid data clocking
Minimum time from clock edge to MODE
with valid data clocking
10k
Logic state change in DOUT on active
SCLK edge
IN
OUT
OUT
IN
to AGND, C L = 100pF, A
A
= 0.5V step
= 0.5V
= +25°C. Specifications over temperature limits are guaranteed by design.
pulldown to AGND, 0.5V step
= 0.5V step
= 0.5V, 1k pulldown to AGND
CONDITIONS
V
V
DD
DD
S
) specification. Switching transient is a result of updat-
= +5V
= +3V
V
= +1V/V, and T
IN
_ = V
OSDFILL
A
MIN
= T
100
100
100
100
100
100
100
100
100
_ = 0 for dual supplies, V
MIN
to T
TYP
200
300
200
30
30
40
60
MAX
V
) and adding output
, unless otherwise
MAX
200
450
200
800
100
300
600
800
UNITS
IN
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
_ =
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