MAX4357 Maxim, MAX4357 Datasheet - Page 28

• Manufacturer Part Number: MAX4357
• Description: The MAX4357 is a 32 x 16 highly integrated video crosspoint switch matrix with input and output buffers
• Manufacturer: Maxim

32 x 16 Nonblocking Video Crosspoint Switch
with I/O Buffers
28
2, 4, 6, 8, 10, 12, 14, 16, 18,
66, 100, 102, 103, 104, 106,
108, 110, 112, 114, 116, 118,
3, 5, 7, 9, 11, 13, 15, 17, 19,
20, 22, 24, 26, 28, 30, 32,
34, 36, 38, 40, 42, 44, 65,
21, 23, 25, 27, 29, 31, 33,
68, 70, 72, 74, 76, 78, 80,
82, 84, 86, 88, 90, 92, 94,
37, 39, 41, 43, 105, 107,
109, 111, 113, 115, 117,
119, 121, 123, 125, 127
120, 122, 124, 126, 128
35, 67, 71, 75, 79, 83,
______________________________________________________________________________________
1, 69, 73, 77, 81,
85, 89, 93, 97
87, 91, 95, 99
58–63, 101
47–50
96, 98
PIN
45
46
51
52
53
54
55
56
57
64
OUT0–OUT15
IN0–IN31
UPDATE
RESET
NAME
AGND
DGND
A3–A0
MODE
AOUT
DOUT
SCLK
N.C.
V
V
DIN
V
CE
CC
DD
EE
Negative Analog Supply. Bypass each pin with a 0.1µF capacitor to AGND.
Connect a single 10µF capacitor from one V
Analog Ground
Buffered Analog Inputs
Positive Analog Supply. Bypass each pin with a 0.1µF capacitor to AGND.
Connect a single 10µF capacitor from one V
Digital Ground
Address Recognition Output. AOUT drives low after successful chip address
recognition.
Address Programming Inputs. Connect to DGND or V
Individual Output Address Mode (Table 3).
Serial Data Output. In Complete Matrix Mode, data is clocked through the 112-bit
Matrix Control Shift register. In Individual Output Address Mode, data at DIN
passes directly to DOUT.
Serial Clock Input
Clock Enable Input. Drive low to enable the serial data interface.
S er i al Inter face M od e S el ect Inp ut. D r i ve hi g h for C om p l ete M atr i x M od e ( M od e 1) ,
or drive low for Individual Output Address Mode (Mode 0).
Asynchronous Reset Input/Output. Drive RESET low to initiate hardware reset. All
matrix settings are set to power-up defaults and all analog outputs are disabled.
Additional power-on reset delay may be set by connecting a small capacitor from
RESET to DGND.
Update Input. Drive UPDATE low to transfer data from mode registers to the
matrix switch.
Serial Data Input. Data is clocked in on the falling edge of SCLK.
No Connection. Not internally connected. Connect to AGND.
Digital Logic Supply. Bypass V
Buffered Analog Outputs. Gain is individually programmable for A V = +1V/V or
A V = +2V/V through the serial interface. Outputs may be individually disabled
(high impedance). On power-up, or assertion of RESET, all outputs are disabled.
DD
with a 0.1µF capacitor DGND.
FUNCTION
EE
CC
pin to AGND.
pin to AGND.
Pin Description
DD
to select the address for