MAX9124 Maxim, MAX9124 Datasheet
MAX9124
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MAX9124 Summary of contents
Page 1
... The MAX9124 accepts four LVTTL/LVCMOS input levels and translates them to LVDS output signals. Moreover, the MAX9124 is capable of setting all four outputs to a high-impedance state through two enable inputs, EN and EN, thus dropping the device to an ultra-low-power state of 16mW (typ) during high impedance ...
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... SO (derate 8.7mW/°C above +70°C)................696mW Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability ...
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... Enable Time Z to High Enable Time Z to Low Maximum Operating Frequency (Note 11) Note 1: Maximum and minimum limits over temperature are guaranteed by design and characterization. Devices are 100% tested +25°C. A Note 2: Currents into the device are positive, and current out of the device is negative. All voltages are referenced to ground except V ...
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Quad LVDS Line Driver (T = +25°C) A SINGLE-ENDED OUTPUT VOLTAGE vs. LOAD RESISTANCE (R = 50Ω TO 400Ω) L 2.10 1.90 1.70 1. +3. +3.0V CC 1.10 0.90 0.70 0.50 0.30 50 100 ...
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... This device accepts LVTTL/LVCMOS input levels and translates them to LVDS output signals. The MAX9124 generates a 2.5mA to 4.0mA output cur- rent using a current-steering configuration. This current- steering approach induces less ground bounce and no shoot-through current, enhancing noise margin and sys- tem speed performance ...
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... OS IN_ OUT_ - OUT_+ V DIFF 20% Figure 3. Driver Propagation Delay and Transition Time Waveforms V CC IN_ GND EN GENERATOR EN 50Ω 1/4 MAX9124 Figure 4. Driver High-Impedance Delay Test Circuit 6 _______________________________________________________________________________________ GENERATOR Figure 2. Driver Propagation Delay and Transition Time Test Circuit 1.5V 1. PLHD PHLD 0 DIFFERENTIAL ...
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EN WHEN WHEN OUT_+ WHEN IN_ = V CC OUT_- WHEN IN_ = 0 OUT_+ WHEN IN_ = 0 OUT_- WHEN IN_ = V CC Figure 5. Driver High-Impedance Delay Waveform Functional ...
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Quad LVDS Line Driver 8 _______________________________________________________________________________________ Package Information ...
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... Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 _____________________ 9 © ...