MAX9205 Maxim, MAX9205 Datasheet
MAX9205
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MAX9205 Summary of contents
Page 1
... Upon power-up, a synchroniza- tion mode is activated, which is controlled by two SYNC inputs, SYNC1 and SYNC2. The MAX9205 can lock to a 16MHz to 40MHz system clock, while the MAX9207 can lock to a 40MHz to 66MHz system clock. The serializer output is held in ...
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... IN0 to IN9 = PWRDN = EN = high 0.8V, PWRDN OUT+ OUT- _VCC 0V 3.6V OX _VCC OUT+ OUT- MAX9205 R = 27_ or 50_ L I worst-case pattern CC (Figures 2, 4) MAX9207 PWRDN = low I CCX = -40°C to +85°C. Typical values are MIN TYP MAX 2 GND 0.8 -20 ...
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... Low-State Delay SYNC Pulse Width t PLL Lock Time Bus LVDS Bit Width Serializer Delay _______________________________________________________________________________________ 10-Bit Bus LVDS Serializers = 27Ω ±1% or 50Ω ±1 10pF CONDITIONS MAX9205 TCCF MAX9207 MAX9205 t TCP MAX9207 Figure 3 CLKT t JIT Figure 4 LHT ...
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... Typical Operating Characteristics = 10pF +25°C, unless otherwise noted.) A 3.6 = -40°C to +85°C. Typical values are MIN TYP MAX 200 140 140 140 WORST-CASE PATTERN SUPPLY CURRENT vs. SUPPLY VOLTAGE TCLK = 40MHz MAX9205 10 3.0 3.3 3.6 SUPPLY VOLTAGE (V) = AVCC UNITS ps (pk-pk) ps (RMS) ...
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... LVCMOS/LVTTL Logic Input. High selects a TCLK rising-edge data strobe. Low selects a TCLK 13 TCLK_R/F falling-edge data strobe. LVCMOS/LVTTL Reference Clock Input. The MAX9205 accepts a 16MHz to 40MHz clock. The MAX9207 accepts a 40MHz to 66MHz clock. TCLK provides a frequency reference to the PLL and 14 TCLK strobes parallel data into the input latch. ...
Page 6
... When the supply voltage reaches 2.35V, the PLL starts to lock to a local refer- ence clock (16MHz to 40MHz for MAX9205 and 40MHz to 66MHz for MAX9207). The reference clock, TCLK, is provided by the system. A serializer locks within 2049 cycles of TCLK ...
Page 7
... Termination with a single resistor at the end of a point- to-point link typically provides acceptable performance. However, the MAX9205/MAX9207 output levels are specified for double-terminated point-to-point and mul- tipoint applications. With a single 100Ω termination, the output swing is larger. ...
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Bus LVDS Serializers OUT+ OUT- Figure 4. Output Load and Transition Times TCLK IN_ TIMING SHOWN FOR TCLK_R/F = LOW Figure 5. Data Input Setup and Hold Times OUT± Figure 6. High-Impedance ...
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PWRDN TCLK OUT± HIGH IMPEDANCE SYNC 1 = SYNC 2 = LOW EN = HIGH TCLK_R/F = HIGH Figure 7. PLL Lock Time and PWRDN High-Impedance Delays IN IN0 - IN9 SYMBOL TCLK 1.5V OUT± TCLK_ ...
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... The double termination typically PARALLEL DATA IN MAX9205 MAX9207 Figure 11. Double-Terminated Point-to-Point ASIC ASIC MAX9205 MAX9207 Figure 12. Multidrop 10 ______________________________________________________________________________________ Topologies reduces reflections compared to a single 100Ω termi- nation. A single 100Ω termination at the deserializer input is feasible and will make the differential signal swing larger ...
Page 11
... Multiple serializers and deserializers bused over a dif- ferential serial connection on a backplane are shown in Figure 14. The second serializer can be a backup to ASIC MAX9205 MAX9207 MAX9150 REPEATER 100Ω 100Ω ...
Page 12
... RoHS status. PACKAGE TYPE 28 SSOP ASIC ASIC MAX9206 MAX9208 Functional Diagram OUT+ 10 IN_ OUT- TCLK_R/F TCLK EN TIMING AND PLL CONTROL PWRDN SYNC 1 SYNC 2 MAX9205 MAX9207 Package Information PACKAGE OUTLINE CODE NO. PATTERN NO. A28+4 21-0056 MAX9206 MAX9208 54Ω LAND 90-0095 ...
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... Updated Ordering Information, Absolute Maximum Ratings, and Package Information Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. ...