MAX9214 Maxim, MAX9214 Datasheet
MAX9214
Available stocks
Related parts for MAX9214
MAX9214 Summary of contents
Page 1
... DC balance, which allows isolation between a serializer and deserializer using AC-coupling. Each deserializer decodes data transmitted by one of MAX9209/MAX9213 serializers. The MAX9210/MAX9214 have rising-edge output strobes, and when DC balance is not programmed, are compatible with non-DC-balanced 21-bit deserializers such as the DS90CR216A and DS90CR218A. The MAX9220/MAX9222 have falling-edge output strobes ...
Page 2
... -100µA OH RxCLK OUT MAX9210/ OH MAX9220 I = -2mA RxOUT_ OH MAX9214/MAX9222 I = 100µA OL RxCLK OUT MAX9210 MAX9220 I = 2mA OL RxOUT_ MAX9214/MAX9222 PWRDWN = low -0. 0.3V OUT_ CCO = 1.5kΩ 100pF 330Ω 150pF 2kΩ 330pF 0.05V to ID MIN TYP MAX 2 ...
Page 3
... MAX9220 DC- balanced mode CCO MAX9214/ = 3.0V to 3.6V, MAX9222 Figure 2 I MAX9210/ CCW MAX9220 C = 8pF, worst L case pattern, non-DC-balanced mode CCO = 3.0V to 3.6V, MAX9214/ Figure 2 MAX9222 PWRDWN = low I CCZ 21-Bit Deserializers MIN TYP MAX -10 -40 -5 -20 -10 -40 -28 -75 -14 -37 -28 -75 50 -50 -25 ...
Page 4
... RxCLK OUT 0.9V , CCO Figure 3 MAX9214/MAX9222 RxOUT_ 0.9V MAX9210/ CCO to MAX9220 RxCLK OUT 0.1V , CCO Figure 3 MAX9214/MAX9222 8MHz 16MHz DC-balanced mode, Figure 4 (Note 6) 34MHz 66MHz 10MHz 20MHz Non-DC-balanced mode, Figure 4 (Note 6) 40MHz 85MHz Figures 5a, 5b Figures 5a, 5b Figures 5a, 5b Figures 5a, 5b Figures 6a, 6b ...
Page 5
... WORST-CASE PATTERN AND PRBS SUPPLY CURRENT vs. FREQUENCY MAX9220 NON-DC-BALANCED MODE WORST-CASE PATTERN PRBS FREQUENCY (MHz) WORST-CASE PATTERN SUPPLY CURRENT vs. FREQUENCY MAX9214 NON-DC-BALANCED MODE FREQUENCY (MHz) OUTPUT TRANSITION TIME vs. OUTPUT SUPPLY VOLTAGE (V ) CCO 7 MAX9220 ...
Page 6
... PLL Ground PLL Supply Voltage 5V Tolerant LVTTL/LVCMOS Power-Down Input. Internally pulled down to GND. Outputs are high impedance when PWRDWN = low or open. Parallel Rate Clock Single-Ended Output. MAX9210/MAX9214, rising edge strobe. MAX9220/MAX9222, falling edge strobe. Channel 0 Single-Ended Outputs Output Supply Voltage Channel 1 Single-Ended Outputs ...
Page 7
... In DC-balanced mode, 9 bits are deserialized every clock cycle (7 data bits + 2 DC- balance bits). The highest data rate in DC-balanced mode for the MAX9214 and MAX9222 is 66MHz 594Mbps. In non-DC-balanced mode, the maximum data rate is 85MHz 595Mbps. ...
Page 8
Programmable DC-Balance 21-Bit Deserializers RxOUT_ OR RxCLK OUT 8pF Figure 3. Output Load and Transition Times IDEAL SERIAL BIT TIME RSKM RSKM IDEAL MIN MAX INTERNAL STROBE Figure 4. LVDS Receiver Input Skew Margin RCIP RxCLK OUT 2.0V 2.0V 0.8V ...
Page 9
... Two complementary bits are appended to each group of 7 parallel input data bits to indicate to the MAX9210/ MAX9214/MAX9220/MAX9222 deserializers whether the data bits are inverted (see Figures 9 and 10). The deserializer restores the original state of the parallel data ...
Page 10
... The RC network for an AC-coupled link consists of the LVDS receiver termination resistor (R output resistor (R ), and the series AC-coupling capac- O itors (C). The RC time constant for two equal-value MAX9210 MAX9214 MAX9220 MAX9222 TRANSMISSION LINE TxOUT RxIN 100Ω 100Ω 100Ω ...
Page 11
... where jitter (s transition time ( 100%). droop (% of signal amplitude). Jitter due to 2% droop and assumed 1ns transition time is: 21-Bit Deserializers MAX9210 MAX9214 MAX9220 MAX9222 RxIN 7 1:( 1:( RxOUT 7 1:( PWRDWN PLL RxCLK OUT 3:21 DESERIALIZER ) is the period of the parallel clock divided by ...
Page 12
... Equation 1 altered for four series capacitors (Figure 13) is DSV)/( The MAX9210/MAX9214/MAX9220/MAX9222 have fail- safe LVDS inputs in non-DC-balanced mode (Figure 1). Fail-safe drives the outputs low when the correspond- ing LVDS input is open, undriven and shorted, or undriven and parallel terminated. The fail-safe on the LVDS clock input drives all outputs low ...
Page 13
... LVDS inputs, and digital signals is recom- mended. The MAX9210/MAX9214/MAX9220/MAX9222 ESD toler- ance is rated for IEC 61000-4-2, Human Body Model and ISO 10605 standards. IEC 61000-4-2 and ISO 10605 specify ESD tolerance for electronic systems. The IEC ...
Page 14
... Absolute Maximum Ratings for maximum package power dissipation capacity and temperature derating. Rising- or Falling-Edge Output Strobe The MAX9210/MAX9214 have a rising-edge output strobe, which latches the parallel output data into the next chip on the rising edge of RxCLK OUT. The MAX9220/MAX9222 have a falling-edge output strobe, which latches the parallel output data into the next chip on the falling edge of RxCLK OUT ...
Page 15
... STROBE RxIN2- LVDS CLOCK RECEIVER RxCLK IN+ 7x/9x PLL RxCLK IN- DCB/NC PWRDWN Chip Information MAX9210 TRANSISTOR COUNT: 10,248 MAX9214 TRANSISTOR COUNT: 10,248 MAX9220 TRANSISTOR COUNT: 10,248 MAX9222 TRANSISTOR COUNT: 10,248 PROCESS: CMOS ______________________________________________________________________________________ Programmable DC-Balance DATA TOP VIEW CHANNEL 0 RxOUT0–6 SERIAL-TO- PARALLEL ...
Page 16
... Programmable DC-Balance 21-Bit Deserializers (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information www.maxim-ic.com/packages.) N MARKING AAA TOP VIEW SIDE VIEW NOTES: 1. DIMENSIONS D & E ARE REFERENCE DATUMS AND DO NOT INCLUDE MOLD FLASH. ...
Page 17
... Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 17 © ...