MAX9217 Maxim, MAX9217 Datasheet
MAX9217
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MAX9217 Summary of contents
Page 1
... ESD tolerance is specified for ISO 10605 with ±10kV contact discharge and ±30kV air discharge. The MAX9217 operates from a +3.3V core supply and features a separate input supply for interfacing to 1.8V to 3.3V logic levels. This device is available in 48-lead Thin QFN and LQFP packages and is specified from -40° ...
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... Thin QFN (derate 37mW/°C above +70°C) .2963mW Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability ...
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DC ELECTRICAL CHARACTERISTICS (continued) = 100Ω ±1%, PWRDWN = high +3.0V to +3.6V, R CC_ +3.3V +25°C.) (Notes 1, 2) CC_ A PARAMETER SYMBOL Differential Output Resistance Worst-Case Supply Current Power-Down Supply ...
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... Note 2: Maximum and minimum limits over temperature are guaranteed by design and characterization. Devices are production tested +25°C. A Note 3: All LVTTL/LVCMOS inputs, except PWRDWN at ≤ 0.3V or ≥ V Note 4: AC parameters are guaranteed by design and characterization and are not production tested. Limits are set at ±6 sigma. ...
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PIN NAME 1, 13, 37 GND Input Buffer Supply and Digital Supply Ground Input Buffer Supply Voltage. Bypass to GND with 0.1µF and 0.001µF capacitors in parallel CCIN close to the device as possible, with the smallest ...
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... Figure 1. LVDS DC Output Load and Parameters 6 _______________________________________________________________________________________ 1 DC BALANCE/ INPUT LATCH PAR-TO-SER ENCODE 0 PLL TIMING AND CONTROL OUT+ OUT ((OUT+) + (OUT-)) / 2 V (+) OS Δ (+) - (+) OD Δ (+) - Functional Diagram OUT+ OUT- CMF MAX9217 GND V (-) OS | (-) V (-) OD | (-) ...
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PCLK_IN t F Figure 2. Parallel Clock Requirements (OUT+) - (OUT-) Figure 3. Output Rise and Fall Times PCLK_IN RGB_IN[17:0] CNTL_IN[8:0] DE_IN Figure 4. Synchronous Input Timing _______________________________________________________________________________________ 27-Bit, 3MHz-to-35MHz DC-Balanced LVDS Serializer LOW OUT+ OUT- C ...
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DC-Balanced LVDS Serializer RGB_IN CNTL_IN PCLK_IN OUT_ Figure 5. Serializer Delay PWRDWN HIGH-Z (OUT+) - (OUT-) PCLK_IN Figure 6. PLL Lock Time PWRDWN (OUT+) - (OUT-) PCLK_IN Figure 7. Power-Down Delay 8 _______________________________________________________________________________________ EXPANDED ...
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... OUT+ ((OUT+) + (OUT-)) / 2 Figure 8. Peak-to-Peak Output Offset Voltage Detailed Description The MAX9217 DC-balanced serializer operates at a parallel clock frequency of 3MHz to 35MHz, serializing 18 bits of parallel video data RGB_IN[17:0] when the data enable input DE_IN is high bits of parallel control data CNTL_IN[8:0] when DE_IN is low. The ...
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... Frequency-Range Setting RNG[1:0] The RNG[1:0] inputs select the operating frequency range of the MAX9217 serializer. An external clock with- in this range is required for operation. Table 3 shows the selectable frequency ranges and corresponding data rates for the MAX9217. ...
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... Figure 10. AC-Coupled Serializer and Deserializer with Two Capacitors per Link RGB_IN 1 0 CNTL_IN DE_IN PCLK_IN TIMING AND RNG0 PLL CONTROL RNG1 PWRDWN MAX9217 CERAMIC RF SURFACE-MOUNT CAPACITOR Figure 11. AC-Coupled Serializer and Deserializer with Four Capacitors per Link ______________________________________________________________________________________ 27-Bit, 3MHz-to-35MHz DC-Balanced LVDS Serializer V CC 130Ω 130Ω * OUT IN * 82Ω ...
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... The integrated 100Ω output termination is made up of two 50Ω resistors in series. The junction of the resistors is connected to the CMF pin for connecting an optional common-mode filter capacitor. Connect the filter capacitor to ground close to the MAX9217 as shown in Figure 13. The capacitor shunts common-mode switch- ing current to ground to reduce EMI. 12 ______________________________________________________________________________________ Table 3 ...
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... DC-Balanced LVDS Serializer Power-Supply Circuits and Bypassing The MAX9217 has isolated on-chip power domains. The digital core supply ( are isolated but have a common ground (GND). CCIN The PLL has separate power and ground (V ...
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... DC-Balanced LVDS Serializer Separate the LVTTL/LVCMOS inputs and LVDS output to prevent crosstalk. A four-layer PCB with separate layers for power, ground, and signals is recommended. The MAX9217 ESD tolerance is rated for Human Body Model, Machine Model, and ISO 10605. ISO 10605 R D 1MΩ ...
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... Added automotive qualified part to Ordering Information Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 15 © ...