MAX9258 Maxim, MAX9258 Datasheet
MAX9258
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MAX9258 Summary of contents
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... Rev 1; 3/09 Fully Programmable Serializer/Deserializer General Description The MAX9257 serializer pairs with the MAX9258 deseri- alizer to form a complete digital video serial link. The MAX9257/MAX9258 feature programmable parallel data width, parallel clock frequency range, spread spectrum, and preemphasis. An integrated control channel trans- fers data bidirectionally at power-up during video blank- ing over the same differential pair used for video data ...
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... For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability ...
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Fully Programmable Serializer/Deserializer MAX9257 DC ELECTRICAL CHARACTERISTICS (continued +3.0V to +3.6V 50Ω ±1%, T CC_ +25°C.) (Notes PARAMETER SYMBOL Low-Level Output Voltage Output Short-Circuit Current 2 I C/UART I/O Input ...
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Fully Programmable Serializer/Deserializer 2 with UART/I C Control Channel MAX9257 DC ELECTRICAL CHARACTERISTICS (continued +3.0V to +3.6V 50Ω ±1%, T CC_ +25°C.) (Notes PARAMETER SYMBOL POWER SUPPLY Worst-Case Supply Current ...
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... Pulse Width of Spike Suppressed in SDA Data Setup Time t Data Hold Time TIMING (Note 8) Maximum SCL Clock Frequency Minimum SCL Clock Frequency Start Condition Hold Time t HD:STA _______________________________________________________________________________________ with UART/I = -40°C to +105°C, unless otherwise noted. Typical values are ...
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... Data Hold Time t HD:DAT Data Setup Time t SU:DAT Setup Time for STOP Condition t SU:STO Bus Free Time MAX9258 DC ELECTRICAL CHARACTERISTICS (V = +3.0V to +3.6V 50Ω ±1%, differential input voltage |V CC_ /2 -40°C to +105°C, unless otherwise noted. Typical values are ...
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... Fully Programmable Serializer/Deserializer MAX9258 DC ELECTRICAL CHARACTERISTICS (continued +3.0V to +3.6V 50Ω ±1%, differential input voltage |V CC_ /2 -40°C to +105°C, unless otherwise noted. Typical values are +25°C.) (Notes PARAMETER SYMBOL V Input Hysteresis (Figure 2) V POWER SUPPLY ...
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... Fully Programmable Serializer/Deserializer 2 with UART/I C Control Channel MAX9258 AC ELECTRICAL CHARACTERISTICS (continued +3.0V to +3.6V 50Ω ±1%, C CC_ / /2 -40°C to +105°C, unless otherwise noted. Typical values are 1.2V +25°C. (Notes 5, 6, and 7) A PARAMETER SYMBOL ...
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... BER CAN BE AS LOW AS 10 CABLE LENGTHS LESS THAN 10m. 400 Control Channel SERIAL LINK SWITCHING PATTERN WITH PREEMPHASIS (BIT RATE = 840MHz, 2m STP CABLE) (PREEMPHASIS = 100%) MAX9258 OUTPUT POWER SPECTRUM vs. PCLK FREQUENCY 20 10kHz BW NO SPREAD 4% SPREAD 2% SPREAD 0 -20 -40 -60 -80 ...
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Fully Programmable Serializer/Deserializer 2 with UART/I C Control Channel PIN NAME TQFN LQFP CCIO 2, 11, 3, 14, GND 19, 34 22, 41 DIN[9:14]/ 3–8 4–9 GPIO[1: GND FPLL CCFPLL ...
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... GND with 0.1µF and 0.001µF capacitors in parallel as close CC to GND CCLVDS LVDS to GND with 0.1µF and 0.001µF capacitors in parallel as CCPLL PLL CCOUT C Control Channel FUNCTION MAX9258 Pin Description . CC with 0.1µF and 0.001µF capacitors in parallel . CCLVDS . CCPLL with a 1kΩ resistor. 11 ...
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... CCSPLL 27 GND SPLL Ground SPLL LVCMOS/LVTTL Control Channel Enabled Output. CCEN asserts high to indicate that control 47 CCEN channel is enabled. 12 ______________________________________________________________________________________ MAX9258 Pin Description (continued) FUNCTION CCOUT is the supply for all output buffers. Bypass V CCOUT . CCOUT . . CCOUT with a 1kΩ resistor. to GND ...
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Fully Programmable Serializer/Deserializer SDO- V (-) OS SDO+ V (-) OD (SDO+) - (SDO-) Figure 1. MAX9257 LVDS DC Output Parameters V OUT V V HYST+ HYST Figure 2. Input Hysteresis ______________________________________________________________________________________ 2 with ...
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Fully Programmable Serializer/Deserializer 2 with UART/I C Control Channel (SDO+) - (SDO-) Figure 4. MAX9257 LVDS Control Channel Output Load and Output Rise/Fall Times PCLK_IN DIN, VSYNC_IN, HSYNC_IN Figure 5. MAX9257 Input Setup and Hold Times 14 ______________________________________________________________________________________ SDO+ SDO- ...
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... NOTE: PCLK_OUT PROGRAMMED FOR RISING LATCH EDGE. Figure 8. MAX9258 Worst-Case Pattern Output ______________________________________________________________________________________ 2 with UART/I C Control Channel EXPANDED TIME SCALE N+2 N+3 N-1 t PSD1 FIRST BIT LOW MAX9258 Figure 9. MAX9258 Output Rise and Fall Times N+4 N LAST BIT IHMIN t HIGH V ILMAX C L SINGLE-ENDED OUTPUT LOAD 0 CCOUT 0 ...
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... Fully Programmable Serializer/Deserializer 2 with UART/I C Control Channel PCLK_OUT Figure 10. MAX9258 Clock Output High and Low Time PCLK_OUT DOUT, VSYNC_OUT, HSYNC_OUT, LOCK Figure 11. MAX9258 Output Data Valid Times V PD IHMIN t PUD POWERED DOWN Figure 12. MAX9258 Power-Up Delay 16 ______________________________________________________________________________________ t LOW V OLMAX t DVB V OHMIN ...
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... FIRST BIT DOUT, HSYNC_OUT, PARALLEL WORD N-2 VSYNC_OUT PCLK_OUT NOTE: PCLK_OUT PROGRAMMED FOR RISING LATCHING EDGE. Figure 14. MAX9258 Serial-to-Parallel Delay +25mV -25mV NOTE ONE SERIAL BIT. TIME INPUT IS MEASURED DIFFERENTIALLY (V Figure 15. MAX9258 Jitter Tolerance 1 0.8V OD(+) 0 0.2V OD(+) (SDO+) - (SDO-) t R1A 0 ...
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... UART deserializing programmable 10, 12, 14, 16, and 18 bits parallel data during the video phase. The MAX9257/ MAX9258 have two phases of operation: video and control channel (Figures 19 and 20). During the video phase, the MAX9257 accepts parallel video data and transmits serial encoded data over the LVDS link. The MAX9258 accepts the encoded serial LVDS data and converts it back to parallel output data ...
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... VSYNC initiates the control channel phase. Nonactive edge of VSYNC can transition at any time after MAX9257 spread is not enabled and T 0.5/f when enabled. At the end of video phase, the SSM MAX9258 drives CCEN high to indicate to the ECU that 8t T VSYNC_IN VIDEO SDI/O± SDI/O± CCEN Figure 19 ...
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... PRBSEN = 0, PRBS test disabled 0xFA MAX9257 address = 1111 1010 0xFF End frame = 1111 1111 0xF8 MAX9258 address = 1111 1000 INTMODE = 0, interface with peripheral is UART INTEN = 0, interface with peripheral is disabled 0x00 FAST = 0, UART bit rate = DC to 4.25Mbps CTO = 000, never come back ...
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... Table 1. MAX9257 Power-Up Default Register Map (continued) REGISTER REGISTER NAME ADDRESS (hex) REG11 0x0B REG12 0x0C REG13 0x0D REG14 0x0E Table 2. MAX9258 Power-Up Default Register Map (see the MAX9258 Register Table ) REGISTER REGISTER NAME ADDRESS (hex) REG0 0x00 REG1 0x01 REG2 0x02 REG3 0x03 ...
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... SDO+, SDO- SCL/TX, SDA/RX, REM Table 4. MAX9258 I/O Supply INPUTS/OUTPUTS All inputs and outputs SDI+, SDI- word width, serial frequency range, parity, spread-spec- trum, and pixel clock frequency range ( see the MAX9257 Register Table and the MAX9258 Register Table) . SUPPLY V CCIO V CCLVDS V CC ...
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Fully Programmable Serializer/Deserializer Table 5. Serial Video Data Format for 20-Bit Serial-Word Length (Parallel-Word Width = 18) BIT NAME EN0 EN1 HSYNC VSYNC D0 Table 6. Serial Video Data Format for 18-Bit Serial-Word Length (Parallel-Word Width ...
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... PWIDTH (REG0[2:0 the MAX9258 tracks and passes the spread to its clock and data outputs. The MAX9257/MAX9258 are both center spread (Figure 21). The control channel does not use spread spectrum, but has slower transition times. MAX9258 Spread Spectrum The MAX9258 features a programmable spread-spec- trum clock and data outputs for reduced EMI ...
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... VSYNC: The MAX9257 and the MAX9258 enter control channel on the falling edge of VSYNC. The default reg- ister settings are VSYNC active falling edge for both the MAX9257 and the MAX9258. If the VSYNC active edge is programmed for rising edge at the MAX9257, the MAX9258 VSYNC active edge must also be pro- grammed for rising edge to reproduce VSYNC rising edge at the MAX9258 output ...
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... LOCK is high impedance when the MAX9258 is locked to the MAX9257 and remains high under the locked condition. When the devices are in shutdown, the channel is not locked and LOCK goes high impedance, is pulled high, and should be ignored ...
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... LOCK outputs together and use a single pullup resistor to pull up all the lines high. LOCK is high if all the devices are locked. Do the same thing for ERROR; ERROR is low if any MAX9258 reports errors. Base Mode and Bypass Mode (Basics) In the control channel phase, there are two modes: base and bypass ...
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... The ETO (end timeout) timer closes the control channel if the ECU stops communicating for the ETO timeout period. Configure register REG3[7:4] for both the MAX9257 and the MAX9258 to select the divide ratio (ETODIV) for the ETO clock as a function of the pixel clock (Table 25). The timeout period is determined by ...
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... DOUT_ T1 = TIME TO ENTER CONTROL CHANNEL T4 = ETO TIMEOUT PERIOD T5 = CONTROL CHANNEL EXIT TIME DUE TO ETO HSK = HANDSHAKING BETWEEN MAX9257 AND MAX9258 Figure 23. Control Channel Closing Due to ETO Timeout counter bits REG3[3:0] that increment once every ETO clock period. Write to REG3[3:0] to determine the counter end time ...
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... The MAX9258 features a proprietary VCO lock that prevents frequency drift while in the control chan- nel for extended periods of time. If MAX9257 receives the lock frame, it understands that the MAX9258 locked state and sends a short training sequence. If the lock frame is not received by the MAX9257, it assumes that the MAX9258 is not locked and sends a long train- ing sequence ...
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... UART error register (REG13). ECU must use end frame to the close control channel for the MAX9257 to report back UART and I MAX9258. Whenever one of the bits in the UART error register is 1, ERROR asserts low. The UART error regis- ter is reset when ECU reads it, and ERROR deasserts high immediately if UART errors were the only reason that ERROR was asserted low ...
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... The default method to reset errors is to read the respec- tive error registers in the MAX9258 (registers 10, 11, and 13). If errors were present before the next control chan- nel, the error count gets incremented to the previous number ...
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... MAX9257/ MAX9258. When the control channel is open, the MAX9258 continues outputting the pixel clock while HSYNC and video data are held at the last value. If spread is enabled on the MAX9258, the pixel clock is spread. ______________________________________________________________________________________ with UART/I ...
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... BYPASS MODE CHANNEL T1 = TIME TO ENTER CONTROL CHANNEL T2 = STO TIMER T3 = CTO TIMER T4 = ETO TIMER T5 = CONTROL CHANNEL EXIT TIME HSK = HANDSHAKING BETWEEN THE MAX9257 & THE MAX9258 = TIMER RESET Figure 24. CTO Timing UART-to-I 2 The UART-to-I C converter accepts UART read or write packets issued by the ECU and converts them master protocol when in base mode ...
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... UART Frame Format The UART frame used to program the MAX9257 and the MAX9258 has a low start bit, eight data bits, an even parity bit and a high stop bit. The data following the start bit is the LSB. With even parity, when there are an odd number the data bits (D0 through D7) the parity bit is set to 1 ...
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... In bypass mode, the allowed data rate 10Mbps (Table 29). For data rates faster than 4.25Mbps in bypass mode, REG8[5] in MAX9257 and REG7[5] in MAX9258 must be set high. Set the control channel data rate in base mode by writ- ing to REG8[1:0] in the MAX9257 and REG7[1:0] in the MAX9258 ...
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... C Timing counted in the MAX9258 PRBSERR register (REG12 communication and the ERROR output on the MAX9258 goes low. To start the test, the ECU writes PRBSEN bit of both the MAX9257 and the MAX9258. The PRBS test can Data Rates Greater than 400kbps ...
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... MAX9257. In the MAX9258, a 16-bit parity error counter logs parity errors. The ERROR out- put on the MAX9258 goes low if parity errors exceed a programmable threshold. AC-Coupling Benefits AC-coupling increases the input voltage of the LVDS receiver to the voltage rating of the capacitor ...
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... All single-ended inputs and outputs on the MAX9257 are powered from V the MAX9258 are powered from V V CCOUT ply. The input levels or output levels scale with these supply rails. Separate the LVCMOS/LVTTL signals and LVDS signals to prevent crosstalk. A four-layer PCB with separate lay- ers for power, ground, LVDS, and digital signals is rec- ommended. Layout PCB traces for 100Ω ...
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... HSYNC and VSYNC, excludes DCB, INV, and parity bits) 000 = 10 PWIDTH 001 = 12 010 = 14 011 = 16 Spread-spectrum setting For PRATE ranges 00, 01: all spread options possible For PRATE ranges 10, 11: maximum spread is 2% SPREAD 000 = Off (default) 001 = 1.5% 010 = 1.75% 011 = 2% Reserved (set to 11111) Control channel start timeout divider ...
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... Bypass filter PLL BYPFPLL 0 = active (default bypass Reserved (set to 0) PRBS test enable PRBSEN 0 = disabled (default enabled DEVICEID 7-bit address of MAX9257 Reserved (set End frame to close control channel Reserved (set to 1) DESID 7-bit address ID of MAX9258 Reserved (set Control Channel DESCRIPTION 41 ...
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Fully Programmable Serializer/Deserializer 2 with UART/I C Control Channel ADDRESS BITS DEFAULT 4:2 000 1:0 00 7:4 0000 ...
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Fully Programmable Serializer/Deserializer ADDRESS BITS DEFAULT 7:5 111 12 4:0 00000 7:2 000000 13 1:0 00 7:1 (RO (RO) 15 7:0 (RO) ______________________________________________________________________________________ 2 with UART/I C Control Channel MAX9257 Register Table (continued) NAME LVDS driver preemphasis setting ...
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... Control channel start timeout counter STOCNT Divided pixel clock is used to count up to (STOCNT + 1) MAX9258 Register Table DESCRIPTION 0 = disabled (default enabled 100 = 18 101 = 18 (default) 110 = 18 111 = Off ...
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... PCLK active edge at ECU interface CKEDGE 0 = falling rising (default) Reserved (set to 0000) PRBS test enable PRBSEN 0 = disabled (default enabled DEVICEID 7-bit address of MAX9258 Reserved (set End frame to close control channel Reserved (set to 1) INTMODE Interface mode INTEN Interface enable ...
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... MAX9258 Register Table (continued) NAME Threshold for number of video parity errors (8 LSBs) PATHRLO If the number of errors exceeds this value, ERR pin is asserted. Threshold for number of video parity errors (8 MSBs) PATHRHI If the number of errors exceeds this value, ERR pin is asserted. ...
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... ISO 10605. The ISO 10605 and IEC 61000-4-2 standards specify ESD tolerance for electronic sys- tems. LVDS outputs on the MAX9257 and LVDS inputs on the MAX9258 meet ISO 10605 ESD protection and IEC 61000-4-2 ESD protection. All other pins meet the R D 330Ω ...
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... TO ±4% SPREAD PLL LVDS Tx 1x CLK OUT PARALLEL TO SERIAL + FIFO DIN WIDTH OSC CONTROL UART 2 Tx/ UART-TO-I C BYPASS MAX9258 DESERIALIZER FREQ DETECT PLL LVDS Rx 1x CLK IN SERIAL TO PARALLEL DOUT WIDTH ADDRESS CONTROL UART TX/RX OSC Functional Diagram SDO- 1.2V 100Ω BIAS ...
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... GND LVDS DIN13/GPIO5 8 24 GND DIN14/GPIO6 9 SPLL GND FPLL CCSPLL V 11 CCFPLL 22 GPIO9 N.C. 12 GPIO8 MAX9258 LQFP Pin Configurations N.C. 36 DIN0 35 34 REM V 33 CCLVDS SDO+ 32 SDO- 31 MAX9257 GND 30 LVDS GND 29 SPLL V 28 CCSPLL GPIO9 ...
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... Fully Programmable Serializer/Deserializer 2 with UART/I C Control Channel 10 DATA PCLK SERIAL HSYNC ECU I/O VSYNC LOCK MAX9258 TX μC RX CONTROL UNIT 50 ______________________________________________________________________________________ UP TO 20m CABLE LENGTH 100Ω 100Ω SERIALIZED DIGITAL VIDEO CONTROL CHANNEL Typical Operating Circuit 10 DATA PCLK SERIAL I/O HSYNC CMOS IMAGE ...
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... Fully Programmable Serializer/Deserializer Package Information For the latest package outline information and land patterns www.maxim-ic.com/packages. PACKAGE TYPE PACKAGE CODE 40 TQFN T4055+1 48 LQFP C48+3 ______________________________________________________________________________________ 2 with UART/I C Control Channel DOCUMENT NO. 21-0140 21-0054 51 ...
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... Added automotive qualified part numbers to Ordering Information. Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. ...