74LVTH125MX Fairchild Semiconductor, 74LVTH125MX Datasheet - Page 8
![IC BUFF TRI-ST QD LOW V 14SOIC](/photos/5/44/54490/261-14-soic_sml.jpg)
74LVTH125MX
Manufacturer Part Number
74LVTH125MX
Description
IC BUFF TRI-ST QD LOW V 14SOIC
Manufacturer
Fairchild Semiconductor
Series
74LVTHr
Datasheet
1.74LVTH125MTCX.pdf
(9 pages)
Specifications of 74LVTH125MX
Logic Type
Buffer/Line Driver, Non-Inverting
Number Of Elements
4
Number Of Bits Per Element
1
Current - Output High, Low
32mA, 64mA
Voltage - Supply
2.7 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
14-SOIC (3.9mm Width), 14-SOL
Logic Family
LVT
Number Of Channels Per Chip
4
Polarity
Non-Inverting
Supply Voltage (max)
3.6 V
Supply Voltage (min)
2.7 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
High Level Output Current
- 32 mA
Low Level Output Current
64 mA
Minimum Operating Temperature
- 40 C
Number Of Lines (input / Output)
4 / 3
Output Type
3-State
Propagation Delay Time
4.9 ns at 2.7 V, 3.9 ns at 3.3 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
74LVTH125MXTR
©1998 Fairchild Semiconductor Corporation
74LVTH125 Rev. 1.4.0
Physical Dimensions
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
C. DIMENSIONS ARE EXCLUSIVE OF BURRS, MOLD FLASH,
A. CONFORMS TO JEDEC REGISTRATION MO-153,
B. DIMENSIONS ARE IN MILLIMETERS
E. LANDPATTERN STANDARD: SOP65P640X110-14M
D. DIMENSIONING AND TOLERANCES PER ANSI
F. DRAWING FILE NAME: MTC14REV6
AND TIE BAR EXTRUSIONS
VARIATION AB, REF NOTE 6
Y14.5M, 1982
Figure 3. 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
0.43 TYP
(Continued)
8
0.65
R0.09 min
0.45
1.65
1.00
R0.09min
12.00°
TOP & BOTTOM
6.10
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