FEATURES
APPLICATIONS
BASIC APPLICATION
Multiphase synchronous buck converter for Server
High efficiency and compact VRM
Optimized for Sleep state S3 systems using +5VSB
Notebook Computer and Graphics VR solutions
Ideal for Server Memory applications using +5V
Fixed 5V Gate Drive
Large drivers designed to drive 3nF in < 15ns
Integrated bootstrap diode
Capable of high switching frequencies from 200kHz
Compatible with IR’s patented Active Tri‐Level
Non‐overlap and under voltage protection
Thermally enhanced 10‐pin DFN package
Lead free RoHS compliant package
Low Quiescent power to optimize efficiency
CPUs and DDR Memory VR solutions
with +5V drive
Low‐side driver – 2A source/4A sink
High‐side driver – 2A source/2A sink
Transitions times & Propagation delays < 15ns
up to greater than 1MHz
(ATL) PWM for fastest response to transient
overshoot
Figure 1: CHL8505 Basic Application Circuit
1
December 6, 2011 | FINAL | V1.05
High‐Efficiency 5V MOSFET Gate Driver
DESCRIPTION
The CHL8505 MOSFET is a high‐efficiency gate driver which
can switch both high‐side and low‐side N‐channel external
MOSFETs in a synchronous buck converter. It is intended
for use with IR Digital PWM controllers to provide a total
voltage regulator (VR) solution for today’s advanced
computing applications.
The CHL8505 driver is capable of rapidly switching large
MOSFETs with low R
in high‐efficiency designs. It is uniquely designed to
operate from a 5V source such as a system 5V or 5V
standby voltages in sleep states.
The CHL8505 has a unique circuit which improves drive
strength to the external MOSFETs even with just 5V
supplied at the VDRV pin. This insures faster switching
comparable to drivers designed for +12V drive operation.
The integrated boot diode reduces external component
count. The CHL8505 also features an adaptive non‐overlap
control for shoot‐through protection.
The CHL8505 is configured to drive both the high and low‐
side switches from the patented IR fast Active Tri‐Level
(ATL) PWM signal, which will optimize the turn off time of
individual phases, optimizing transient performance.
PIN DIAGRAM
VDRV
BOOT
PWM
VCC
NC
Figure 2: CHL8505 Package Top View
1
2
3
4
5
dson
and large input capacitance used
Top View
3x3 DFN
Pin 11
GND
CHL8505
10
9
8
7
6
NC
NC
LO_GATE
SWITCH
HI_GATE