IR3502BMPBF International Rectifier, IR3502BMPBF Datasheet - Page 10

• Manufacturer Part Number: IR3502BMPBF
• Description: The IR3502B control IC combined with an XPHASE3 Phase IC provides a full featured and flexible way to implement a complete VR11.0 and VR11.1 power solution.
• Manufacturer: International Rectifier

Specifications of IR3502BMPBF

• Package: 32-Lead MLPQ
• Circuit: X-Phase Control IC
• Switch Freq (khz): 250kHz to 1.5MHz
• Pbf: PbF Option Available

connected to the phase clock input PHSIN of the first phase IC, and PHSOUT of the first phase IC is connected to
PHSIN of the second phase IC, etc. The PHSOUT of the last phase IC is connected back to PHSIN of the control IC.
During power up, the control IC sends out clock signals from both CLKOUT and PHSOUT pins and detects the
feedback at PHSIN pin to determine the phase number and monitor any fault in the daisy chain loop. Figure 4 shows
the phase timing for a four phase converter. The switching frequency is set by the resistor ROSC. The clock frequency
equals the number of phase times the switching frequency.
PWM Operation
The PWM comparator is located in the phase IC. With the PHSIN voltage high, upon receiving the falling edge of a
clock pulse, the PWM latch is set. The PWMRMP voltage begins to increase; the low side driver is turned off, and the
high side driver is turned on after the non-overlap time. When the PWMRMP voltage exceeds the error amplifier’s
output voltage, the PWM latch is reset. This turns off the high side driver and then turns on the low side driver after the
non-overlap time. Along with that, it activates the ramp discharge clamp, which quickly discharges the PWMRMP
capacitor to the output voltage of share adjust amplifier in phase IC until the next clock pulse.
The PWM latch is reset dominant allowing all phases to go to zero duty cycle within a few tens of nanoseconds in
response to a load step decrease. Phases can overlap and go up to 100% duty cycle in response to a load step
increase with turn-on gated by the clock pulses. An error amplifier output voltage greater than the common mode input
range of the PWM comparator results in 100% duty cycle regardless of the voltage of the PWM ramp. This
arrangement guarantees the error amplifier is always in control and can demand 0 to 100% duty cycle as required. It
also favors response to a load step decrease which is appropriate, given the low output to input voltage ratio of most
systems. The inductor current will increase much more rapidly than decrease in response to load transients. The error
amplifier is a high speed amplifier with wide bandwidth and fast slew rate incorporated in the control IC. It is not unity
gain stable.
This control method is designed to provide “single cycle transient response,” where the inductor current changes in
response to load transients within a single switching cycle maximizing the effectiveness of the power train and
minimizing the output capacitor requirements. An additional advantage of the architecture is that differences in the
ground or input voltage at the phases have no effect on operation since the PWM ramps are referenced to VDAC.
Figure 5 depicts PWM operating waveforms under various conditions.
Control IC CLKOUT
(Phase IC CLKIN)
Control IC PHSOUT
(Phase IC1 PHSIN)
Phase IC1
PWM Latch SET
Phase IC 1 PHSOUT
(Phase IC2 PHSIN)
Phase IC 2 PHSOUT
(Phase IC3 PHSIN)
Phase IC 3 PHSOUT
(Phase IC4 PHSIN)
Phase IC4 PHSOUT
(Control IC PHSIN)
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Figure 4 Four Phase Oscillator Waveforms
IR3502B
V3.2