TLE 6368G1 Infineon Technologies, TLE 6368G1 Datasheet - Page 17

• Manufacturer Part Number: TLE 6368G1
• Manufacturer: Infineon Technologies

Specifications of TLE 6368G1

• Packages: P-DSO-36
• Comment: Successor: TLE6368G2
• Vq (max): 5.0 V, 3.3/2.6 V, 3.3/2.6 V
• Iq (max): 1,500.0 mA
• Iq (typ): 30.0 µA
• Output: Linear (Buck Preregulator)

been read in at the DI line becomes the new control word. The DO output switches to
tristate status at this point, thereby releasing the DO bus circuit for other uses. For details
of the SPI timing please refer to Figures 10 to 13.
The SPI will be reset to default values given in the following table “write bit meaning” if
the RAM good flag of Q_LDO1 indicates a cold start (lower output voltage than 3.3V).
The reset will be active as long as the power on reset is present so during the reset delay
time at power up no SPI commands are accepted.
The register content of the SPI - including watchdog timings and reset delay timings - is
maintained if the RAM good flag of Q_LDO1 indicates a warm start (i.e. Q_LDO1 did not
decrease below 3.3V).
2.12.1 Write mode
The following tables show the bit assignment to the different control functions, how to
change settings with the right bit combination and also the default status at power up.
2.12.2 Write mode bit assignment
Figure 8 Write Bit assignment
Write Bit meaning
Function
Not assigned
Tracker 1 to 6 - control:
turn on/off the individual trackers
Power down:
send device to sleep
Data Sheet
BIT
Name
Default
OFF1
WD_
DO
1
assigned
NOT
D1
X
control
T1-
D2
1
control
T2-
D3
1
control
T6-
D4
1
control
T4-
D5
1
control
T5-
D6
1
17
control
T6-
D7
1
Bit
D1
D2
D3
D4
D5
D6
D7
D8
sleep
D8
1
OFF2
WD_
D9
0
Combination
X
0: OFF
1: ON
0: SLEEP
1: NORMAL
reset 1
D10
1
reset 2
D11
1
Rev. 2.2, 2006-12-01
TLE 6368 / SONIC
WD1
D12
0
WD2
D13
0
Default
X
1
1
OFF3
WD_
D14
1
WD_
TRIG
D 15
0