TLE 6251-2G Infineon Technologies, TLE 6251-2G Datasheet - Page 22

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TLE 6251-2G

Manufacturer Part Number
TLE 6251-2G
Description
Manufacturer
Infineon Technologies
Datasheet

Specifications of TLE 6251-2G

Packages
PG-DSO-14
Transmission Ratemax
1.0 Mbit/s
Quiescent Current (max.)
< 30 µA @ 5V standby
Bus Wake-up Capability
Yes
Additional Features
NSTB, WK, EN, NERR, INH, Vio
Wake-up Inputs
Bus wake-up + wake-up pin
Figure 13
7.4
The advantage of the adaptive microcontroller logic is the ratio metrical scaling of the I/O levels depending on the
input voltage at the
voltage of the microcontroller fits to the internal logic levels of the TLE6251-2G.
7.5
The SPLIT output pin is activated during Normal Operation Mode and Receive - Only Mode and deactivated
(SPLIT pin high ohmic) during Sleep Mode and Stand - By Mode. The SPLIT pin is used to stabilize the recessive
common mode signal in Normal Operation Mode and Receive - Only Mode. This is realized with a stabilized
voltage of 0.5 x
Data Sheet
Under - Voltage on
Voltage Adaptation
Split Circuit
V
CC
V
at SPLIT pin.
IO
pin. Connecting the
V
S
V
IO
input to the I/O supply of the microcontroller ensures, that the I/O
22
Rev. 1.0, 2009-05-07
Fail Safe Features
TLE6251-2G

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