A3985SLD-T Allegro Micro Systems, Inc., A3985SLD-T Datasheet
A3985SLD-T
Related parts for A3985SLD-T
A3985SLD-T Summary of contents
Page 1
Features and Benefits ▪ Serial interface for full digital control ▪ Dual full-bridge gate drive for N-channel MOSFETs ▪ Dual 6-bit DAC current reference ▪ Operation over supply voltage range ▪ Synchronous rectification ▪ Cross-conduction protection ...
Page 2
... The above-supply voltage required for the high-side N-channel MOSFETs is provided by a bootstrap capacitor. Efficiency is enhanced by using synchronous rectification and the power FETs Selection Guide Part Number A3985SLD-T Tube, 50 pieces per tube A3985SLDTR-T Tape and reel, 4000 pieces per reel *Contact Allegro for additional packing options ...
Page 3
A3985 +5 V VDD Bandgap V REF REF SDO SDI STR Serial Port SCK WC ENABLE V REF OSC Programmable Divider Oscillator Dual Full-Bridge MOSFET Driver Functional Block Diagram VBB Regulator Phase 1A High-Side Drive V REG 6-bit Low-Side DAC ...
Page 4
A3985 ELECTRICAL CHARACTERISTICS at T Characteristics Supply and Reference Load Supply Voltage Range Load Supply Current Load Supply Idle Current Logic Supply Voltage Range Logic Supply Current Logic Supply Idle Current Regulator Output Bootstrap Diode Forward Voltage Gate Output Drive ...
Page 5
A3985 ELECTRICAL CHARACTERISTICS, continued Characteristics Current Control Blank Time Fixed Off-Time Reference Input Voltage Internal Reference Voltage Current Trip Point Error 2 Reference Input Current 1 Internal Oscillator Frequency Maximum Clock Input Frequency Master Clock Frequency Protection VREG ...
Page 6
A3985 ELECTRICAL CHARACTERISTICS, continued Characteristics Serial Data Timing Serial Clock High Time Serial Clock Low Time Strobe Lead Time Strobe Lag Time Strobe High Time Data Out Enable Time Data Out Disable Time Data Out Valid Time from ...
Page 7
A3985 Basic Operation The A3985 is a highly-configurable dual full-bridge FET driver with built-in digital current control. All features are accessed through a simple SPI (Serial Peripheral Interface) compatible serial port, allowing multiple motors to be con- trolled with as ...
Page 8
A3985 SDI, SCK, STR, SDO These are the serial port interface pins. Data is clocked into SDI by a clock signal on SCK. The data is then latched by a signal on STR. If required, the serial data out pin, ...
Page 9
A3985 through the motor winding and the current sense resistor, RSENSEx. When the voltage across RSENSEx equals the DAC output voltage, the current sense comparator resets the PWM latch, which turns off the source MOSFET (slow decay mode) or the ...
Page 10
A3985 gramming the Fast Decay Time bits in the Control register (Word1, Bits D8 through D11 the device effectively operates in full fast decay mode. Selecting between slow decay and mixed decay is done by programming the Mode ...
Page 11
A3985 to 0 disables Bridge 1, with all drivers off (see Internal PWM Current Control, in the Functional Description section). D7 – Bridge 1 Phase Controls the direction of output cur- rent for Bridge (load S1A 0 L ...
Page 12
A3985 Note that, for t > the device effectively operates in FD OFF full fast-decay mode. D12 and D13 – Master Clock Control An internal oscillator can be used for the timing functions, and if more precise control ...
Page 13
A3985 Current Sensing To minimize inaccuracies in sensing the I level caused by ground-trace IR drops, the sense resistor, RSENSEx, should have an independent return to the supply ground star point. For low-value sense resistors, the IR drops in the ...
Page 14
A3985 Pin-out Diagram Terminal List Table Number ...
Page 15
A3985 9. 38X 0.10 C 0.50 0.22 Copyright ©2005-2007, Allegro MicroSystems, Inc. The products described here are manufactured under one or more U.S. patents or U.S. patents pending. Allegro MicroSystems, Inc. reserves the right to make, ...