AT45DB161 ATMEL Corporation, AT45DB161 Datasheet
AT45DB161
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AT45DB161 Summary of contents
Page 1
... The AT45DB161 is a 2.7-volt only, serial interface Flash memory suitable for in-sys- tem reprogramming. Its 17,301,504 bits of memory are organized as 4096 pages of 528 bytes each. In addition to the main memory, the AT45DB161 also contains two data buffers of 528 bytes each. The buffers allow receiving of data while a page in the main memory is being reprogrammed ...
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... AT45DB161 2 To allow for simple in-system reprogrammability, the AT45DB161 does not require high input voltages for pro- gramming. The device operates from a single power sup- ply, 2.7V to 3.6V, for both the program and read opera- tions. The AT45DB161 is enabled through the chip select ...
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... To start a page read, the 8-bit opcode, 52H, is followed by 24 address bits and 32 don’t care bits. In the AT45DB161, the first two address bits are reserved for larger density devices (see Notes on page 9), the next 12 address bits ...
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... CS pin, the part will first erase the selected page in main memory to all 1s and then program the data stored in the buffer into the specified page in the main memory. Both the erase and the programming of the page AT45DB161 4 are internally self timed and should take place in a maxi- mum time of t ...
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BLOCK ERASE: A block of eight pages can be erased at one time allowing the Buffer to Main Memory Page Pro- gram without Built-In Erase command to be utilized to reduce programming times when writing large amounts of data to ...
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... The device density is indicated using bits 5, 4, and 3 of the status register. For the AT45DB161, the three bits are 1, 0, and 1. The decimal value of these three binary bits does not equate to the device density; the three bits represent a ...
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... This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. AT45DB161 - 2.7V to 3.6V Bit ...
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... Block Erase Time BE t RESET Pulse Width RST t RESET Recovery Time REC Input Test Waveforms and Measurement Levels 2.4V AC DRIVING LEVELS 0.45V < (10 AT45DB161 8 Condition CS, RESET all inputs IH at CMOS levels MHz mA; OUT CMOS levels IN ...
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AC Waveforms Two different timing diagrams are shown below. Waveform 1 shows the SCK signal being low when CS makes a high- to-low transition, and Waveform 2 shows the SCK signal being high when CS makes a high-to-low transition. Both ...
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... Buffer Write CS SI CMD Buffer to Main Memory Page Program (Data from Buffer Programmed into Flash Page Each transition represents 8 bits and 8 clock cycles AT45DB161 10 FLASH MEMORY ARRAY MAIN MEMORY PAGE PROGRAM THROUGH BUFFER 2 MAIN MEMORY PAGE PROGRAM THROUGH BUFFER 1 I/O INTERFACE ...
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Read Operations The following block diagram and waveforms illustrate the various read sequences available. PAGE (528 BYTES) MAIN MEMORY PAGE TO BUFFER 1 BUFFER 1 (528 BYTES) BUFFER 1 READ Main Memory Page Read CS SI CMD ...
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... COMMAND OPCODE Buffer Read CS SCK 1 2 tSU COMMAND OPCODE Status Register Read CS SCK 1 2 tSU HIGH-IMPEDANCE SO AT45DB161 HIGH-IMPEDANCE HIGH-IMPEDANCE COMMAND OPCODE ...
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Detailed Bit-Level Read Timing – Inactive Clock Polarity High Main Memory Page Read CS SCK 1 2 tSU COMMAND OPCODE Buffer Read CS SCK 1 2 tSU COMMAND OPCODE Status Register Read ...
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... • • • X (64th bit) AT45DB161 14 Main Memory Main Memory Page to Buffer 1 Page to Buffer 2 Page to Buffer 1 Transfer Transfer Opcode 53H 55H ...
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Table 2. Buffer 1 to Buffer 1 to Buffer 2 to Main Main Main Memory Memory Memory Page Page Page Program Program Program without with Built with Built- Built-In In Erase In Erase Erase 83H 86H 88H ...
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... A page can be written using either a Main Memory Page Program operation or a Buffer Write operation followed by a Buffer to Main Memory Page Program operation. 3. The algorithm above shows the programming of a single page. The algorithm will be repeated sequentially for each page within the entire sector. AT45DB161 16 START provide address and data ...
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Figure 2. Algorithm for Randomly Modifying Data MAIN MEMORY PAGE PROGRAM Notes preserve data integrity, each page of a DataFlash sector (256 pages per sector) must be updated/rewritten at least once within every 10,000 cumulative page erase/program operations ...
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... Plastic Thin Small Outline Package (TSOP) 25C2 25-Ball, Plastic Chip-Scale Ball Grid Array (CBGA) AT45DB161 18 Ordering Code 0.01 AT45DB161-JC AT45DB161-RC AT45DB161-TC AT45DB161-CC 0.01 AT45DB161-JI AT45DB161-RI AT45DB161-TI AT45DB161-CI Package Type Package Operation Range 32J Commercial 28R ( 28T 25C2 32J Industrial ...
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Packaging Information 32J, 32-Lead, Plastic J-Leaded Chip Carrier (PLCC) Dimensions in Inches and (Millimeters) JEDEC STANDARD MS-016 AE .045(1.14) X 45° PIN NO. 1 IDENTIFY .553(14.0) .547(13.9) .032(.813) .595(15.1) .026(.660) .585(14.9) .050(1.27) TYP .300(7.62) REF .430(10.9) .390(9.90) AT CONTACT POINTS ...