AT87251G2D ATMEL Corporation, AT87251G2D Datasheet
AT87251G2D
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AT87251G2D Summary of contents
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... MHz and 24 MHz • Typical Operating Current MHz MHz Typical Power-down Current: 2 μA • • Low Voltage Version: – 2.7V to 5.5V – 16 MHz 8/16-bit Microcontroller with Serial Communication Interfaces TSC80251G2D TSC83251G2D TSC87251G2D AT80251G2D AT83251G2D AT87251G2D Rev. 4135D–8051–08/05 1 ...
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Typical Operating Current: Typical Power-down Current: 1 μA • • Temperature Ranges: Commercial (0°C to +70°C), Industrial (-40°C to +85°C) • Option: Extended Range (-55°C to +125°C) • Packages: PDIL 40, PLCC 44 and VQFP 44, ...
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Block Diagram P3(A16) P2(A15-8) PSEN# PORTS 0-3 ALE/PROG# EA#/VPP AWAIT# Bus Interface Unit VDD VSS 4135D–8051–08/05 P1(A17) P0(AD7-0) ROM EPROM RAM OTPROM 1 Kbyte 32 KB 16-bit Memory Code 16-bit Memory Address CPU VSS1 VSS2 AT/TSC8x251G2D Timers 0, 1 and ...
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Pin Description Pinout AT/TSC8x251G2D 4 Figure 1. TSC80251G2D 40-pin DIP package P1.0/T2 P1.1/T2EX P1.2/ECI P1.3/CEX0 P1.4/CEX1/SS# P1.5/CEX2/MISO P1.6/CEX3/SCL/SCK/WAIT# P1.7/A17/CEX4/SDA/MOSI/WCLK P3.0/RXD P3.1/TXD P3.2/INT0# P3.3/INT1# P3.4/T0 P3.5/T1 P3.6/WR# P3.7/A16/RD# XTAL2 XTAL1 Figure 2. TSC80251G2D 44-pin PLCC Package P1.5/CEX2/MISO P1.6/CEX3/SCL/SCK/WAIT# P1.7/A17/CEX4/SDA/MOSI/WCLK RST P3.0/RXD ...
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Figure 3. TSC80251G2D 44-pin VQFP Package P1.5/CEX2/MISO P1.6/CEX3/SCL/SCK/WAIT# P1.7/A17/CEX4/SDA/MOSI/WCLK RST P3.0/RXD AWAIT# P3.1/TXD P3.2/INT0# P3.3/INT1# P3.4/T0 P3.5/T1 AT/TSC8x251G2D TSC80251G2D ...
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Table 1. TSC80251G2D Pin Assignment DIP PLCC VQFP Name 1 39 VSS1 P1.0/ P1.1/T2EX P1.2/ECI P1.3/CEX0 P1.4/CEX1/SS P1.5/CEX2/MISO P1.6/CEX3/SCL/SCK/WAIT# ...
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Signals 4135D–8051–08/05 Table 2. Product Name Signal Description Signal Name Type Description th 18 Address Bit Output to memory as 18th external address bit (A17) in extended bus A17 O applications, depending on the values of bits RD0 and RD1 ...
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AT/TSC8x251G2D 8 Table 2. Product Name Signal Description (Continued) Signal Name Type Description Non Maskable Interrupt Holding this pin high for 24 oscillator periods triggers an interrupt. When using the Product Name as a pin-for-pin replacement for a 8xC51 NMI ...
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Table 2. Product Name Signal Description (Continued) Signal Name Type Description Timer 1:0 External Clock Inputs T1:0 I/O When timer 1:0 operates as a counter, a falling edge on the T1:0 pin increments the count. Timer 2 Clock Input/Output ...
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AT/TSC8x251G2D 10 Table 2. Product Name Signal Description (Continued) Signal Name Type Description Output of the on-chip inverting oscillator amplifier XTAL2 O To use the internal oscillator, a crystal/resonator circuit is connected to this pin external oscillator is ...
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Address Spaces Program/Code Memory 4135D–8051–08/05 The TSC80251G2D derivatives implement four different address spaces: • On-chip ROM program/code memory (not present in ROMless devices) • On-chip RAM data memory • Special Function Registers (SFRs) • Configuration array The TSC83251G2D and TSC87251G2D ...
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Data Memory AT/TSC8x251G2D 12 compatibility with the C51 Architecture). When PC increments beyond the end of seg- ment FE:, it continues at the reset address FF:0000h (linearity). When PC increments beyond the end of segment 01:, it loops to the ...
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Special Function Registers 4135D–8051–08/05 The Special Function Registers (SFRs) of the TSC80251G2D derivatives fall into the categories detailed in Table 1 to Table 9. SFRs are placed in a reserved on-chip memory region S: which is not represented in the ...
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AT/TSC8x251G2D 14 Table 4. Serial I/O Port SFRs Mnemonic Name SCON Serial Control SBUF Serial Data Buffer Slave Address SADEN Mask Table 5. SSLC SFRs Mnemonic Name Synchronous Serial SSCON control Synchronous Serial SSDAT Data Synchronous Serial SSCS Control and ...
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Table 7. System Management SFRs Mnemonic Name PCON Power Control POWM Power Management Table 8. Interrupt SFRs Mnemonic Name IE0 Interrupt Enable Control 0 IE1 Interrupt Enable Control 1 IPH0 Interrupt Priority Control High 0 Table 9. Keyboard Interface ...
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Table 10. SFR Descriptions 0/8 1/9 CH F8h 0000 0000 (1) B F0h 0000 0000 CL E8h 0000 0000 (1) ACC E0h 0000 0000 CCON CMOD D8h 00X0 0000 00XX X000 (1) (1) PSW PSW1 D0h 0000 0000 0000 0000 ...
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Configuration Bytes 4135D–8051–08/05 The TSC80251G2D derivatives provide user design flexibility by configuring certain operating features at device reset. These features fall into the following categories: • external memory interface (Page mode, address bits, programmed wait states and the address range ...
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AT/TSC8x251G2D 18 Table 11. Configuration Byte 0 UCONFIG0 WSA1# WSA0# Bit Bit Number Mnemonic Description Reserved 7 - Set this bit when writing to UCONFIG0. 6 WSA1# Wait State A bits Select the number of wait ...
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Table 12. Configuration Byte 1 UCONFIG1 CSIZE - - Bit Number Bit Mnemonic Description On-Chip Code Memory Size bit CSIZE Clear to select on-chip code memory (TSC87251G1D TSC87251G2D product). 7 Set to select ...
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Configuration Byte 1 AT/TSC8x251G2D 20 Table 13. Address Ranges and Usage of RD#, WR# and PSEN# Signals RD1 RD0 P1.7 P3.7/RD A17 A16 0 1 I/O pin A16 1 0 I/O pin I/O pin Read signal for 1 ...
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Instruction Set Summary Notation for Instruction Operands 4135D–8051–08/05 This section contains tables that summarize the instruction set. For each instruction there is a short description, its length in bytes, and its execution time in states (one state time is equal ...
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AT/TSC8x251G2D 22 Table 16. Notation for Immediate Addressing Immediate Address Description #data An 8-bit constant that is immediately addressed in an instruction #data16 A 16-bit constant that is immediately addressed in an instruction #0data16 A 32-bit constant that is immediately ...
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Table 19. Notation for Register Operands Register Description A memory location (00h-FFh) addressed indirectly via byte registers Byte register R0-R7 of the currently selected register bank n Byte register index 0-7 ...
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Size and Execution Time for Instruction Families AT/TSC8x251G2D 24 Table 20. Summary of Add and Subtract Instructions AddADD <dest>, <src>dest opnd ← dest opnd + src opnd SubtractSUB <dest>, <src>dest opnd ← dest opnd - src opnd Add with CarryADDC ...
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If this instruction addresses external memory location, add 2(N+2) to the number of states (N: number of wait states). Table 21. Summary of Increment and Decrement Instructions IncrementINC <dest>dest opnd ← dest opnd + 1 IncrementINC <dest>, <src>dest ...
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AT/TSC8x251G2D 26 Table 22. Summary of Compare Instructions CompareCMP <dest>, <src>dest opnd - src opnd <dest>, (2) Mnemonic <src> Comments Rmd, Rms Register with register WRjd, Word register with word register WRjs DRkd, Dword register with dword register DRks Rm, ...
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ANL <dest>, <src>dest opnd ← dest opnd Λ src opnd (1) Logical AND ORL <dest>, <src>dest opnd ← dest opnd ς src opnd (1) Logical OR XRL <dest>, <src>dest opnd ← dest opnd ∀ src opnd (1) Logical Exclusive OR ...
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Notes: 1. Logical instructions that affect a bit are in Table 27 shaded cell denotes an instruction in the C51 Architecture this instruction addresses an I/O Port (Px 0-3), add 1 to the number ...
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Table 24. Summary of Multiply, Divide and Decimal-adjust Instructions MultiplyMUL AB(B:A) ← (A)×(B) MUL <dest>, <src>extended dest opnd ← dest opnd × src opnd DivideDIV AB(A) ← Quotient ((A) ⁄ (B)) (B) ← Remainder ((A) ⁄ (B)) DivideDIV <dest>, ...
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AT/TSC8x251G2D 30 Table 25. Summary of Move Instructions (1/3) Move to High wordMOVH <dest>, <src>dest opnd Move with Sign extensionMOVS <dest>, <src>dest opnd ← src opnd with sign extend Move with Zero extensionMOVZ <dest>, <src>dest opnd ← src opnd with ...
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Table 26. Summary of Move Instructions (2/3) MOV <dest>, <src>dest opnd ← src opnd (1) Move <dest>, (2) Mnemonic <src> Comments A, Rn Register to ACC Direct address (on-chip RAM or SFR) A, dir8 to ACC ...
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MOV <dest>, <src>dest opnd ← src opnd (1) Move (1) Mnemonic <dest>, <src> Comments MOV Rmd, Rms Byte register to byte register MOV WRjd, WRjs Word register to word register MOV DRkd, DRks Dword register to dword register MOV Rm, ...
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WRj, at WRj MOV Indirect with 16-bit displacement (16M) to word register +dis24 at WRj +dis16, MOV Byte register to indirect with 16-bit displacement (64K WRj +dis16, MOV Word register to indirect with 16-bit displacement (64K) WRj at ...
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AT/TSC8x251G2D 34 Table 27. Summary of Bit Instructions Clear BitCLR <dest>dest opnd ← 0 Set BitSETB <dest>dest opnd ← 1 Complement BitCPL <dest>dest opnd ← ∅ bit AND Carry with BitANL CY, <src>(CY) ← (CY) ∧ src opnd AND Carry ...
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Table 28. Summary of Exchange, Push and Pop Instructions Exchange bytesXCH A, <src>(A) ↔ src opnd ↔ src opnd Exchange DigitXCHD A, <src>(A) 3:0 PushPUSH <src>(SP) ← (SP) +1; ((SP)) ← src opnd; (SP) ← (SP) + size (src ...
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AT/TSC8x251G2D 36 Table 29. Summary of Conditional Jump Instructions (1/2) Jump conditional on statusJcc rel(PC) ← (PC) + size (instr); IF [cc] THEN (PC) ← (PC) + rel <dest>, (1) Mnemonic <src> Comments JC rel Jump if carry JNC rel ...
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Table 30. Summary of Conditional Jump Instructions (2/2) Jump if bitJB <src>, rel(PC) ← (PC) + size (instr); IF [src opnd = 1] THEN (PC) ← (PC) + rel Jump if not bitJNB <src>, rel(PC) ← (PC) + size ...
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AT/TSC8x251G2D 38 Add addresses a Peripheral SFR this instruction addresses an I/O Port (Px 0-3), add 3 to the number of states. Add addresses a Peripheral SFR internal ...
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Table 32. Summary of Call and Return Instructions Absolute callACALL <src>(PC) ← (PC) +2; push (PC) ← src opnd (PC) 10:0 Extended callECALL <src>(PC) ← (PC) + size (instr); push (PC) ← src opnd (PC) 23:0 Long callLCALL <src>(PC) ...
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Programming and Verifying Non-volatile Memory Internal Features EPROM/OTPROM Devices Mask ROM Devices ROMless Devices Security Features AT/TSC8x251G2D 40 The internal non-volatile memory of the TSC80251G2D derivatives contains five differ- ent areas: • Code Memory • Configuration Bytes • Lock Bits ...
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Lock Bit System Encryption Array 4135D–8051–08/05 The TSC87251G2D products implement 3 levels of security for User’s program as described in Table 33. The TSC83251G2D products implement only the first level of security. Level 0 is the level of an erased ...
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Signature Bytes Programming Algorithm AT/TSC8x251G2D 42 To preserve the secrecy of the encryption key byte sequence, the Encryption Array can not be verified. Notes: 1. When a MOVC instruction is executed, the content of the ROM is not encrypted. In ...
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Verify Algorithm 4135D–8051–08/05 • PSEN# and the other control signals have to be released to complete a sequence of programming operations or a sequence of programming and verifying operations. Figure 6. Setup for Programming VDD RST VPP EA#/VPP 100 ms ...
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AT/TSC8x251G2D 44 • Then device is driving the data on Port 2. • possible to alternate programming and verification operation (see Paragraph Programming Algorithm). Please make sure the voltage on the EA# pin has actually been lowered to ...
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AC Characteristics - Commercial & Industrial AC Characteristics - External Bus Cycles Definition of Symbols Timings 4135D–8051–08/05 Table 38. External Bus Cycles Timing Symbol Definitions Signals A Address D Data In L ALE Q Data Out R RD#/PSEN# W WR# ...
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AT/TSC8x251G2D 46 Table 39. Bus Cycles AC Timings; V Symbol Parameter T 1/F OSC OSC T ALE Pulse Width LHLL T Address Valid to ALE Low AVLL T Address hold after ALE Low LLAX (1) T RD#/PSEN# Pulse Width RLRH ...
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Table 40. Bus Cycles AC Timings; V Symbol Parameter T 1/F OSC OSC T ALE Pulse Width LHLL T Address Valid to ALE Low AVLL T Address hold after ALE Low LLAX (1) T RD#/PSEN# Pulse Width RLRH T ...
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Waveforms in Non-Page Mode Figure 8. External Bus Cycle: Code Fetch (Non-Page Mode) AT/TSC8x251G2D 48 ALE PSEN# P0 P2/A16/A17 Note: 1. The value of this parameter depends on wait states. See Table 39 and Table 40. Figure 9. External Bus ...
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Waveforms in Page Mode 4135D–8051–08/05 Figure 10. External Bus Cycle: Data Write (Non-Page Mode) ALE TLHLL(1) WR# T LHAX TAVLL( AVWL1 (1) T AVWL2 P2/A16/A17 Note: 1. The value of this parameter depends on wait states. See Table ...
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AC Characteristics - Real-Time Synchronous Wait State Definition of Symbols AT/TSC8x251G2D 50 Figure 12. External Bus Cycle: Data Read (Page Mode) ALE TLHLL(1) RD#/PSEN# T LHAX (1) T AVLL P2 T AVRL T AVDV2 P0/A16/A17 Note: 1. The value of ...
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Timings Waveforms Figure 14. Real-time Synchronous Wait State: Code Fetch/Data Read State 1 WCLK ALE RD#/PSEN# WAIT Figure 15. Real-time Synchronous Wait State: Data Write State 1 WCLK ALE RD#/PSEN# WAIT 4135D–8051–08/05 Table 42. Real-Time Synchronous ...
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AC Characteristics - Real-Time Asynchronous Wait State Definition of Symbols Timings Waveforms AC Characteristics - Serial Port in Shift Register Mode Definition of Symbols AT/TSC8x251G2D 52 Table 43. Real-Time Asynchronous Wait Timing Symbol Definitions Signals S PSEN#/RD#/WR# Y AWAIT# Table ...
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Timings Waveforms Figure 17. Serial Port Waveforms - Shift Register Mode T XLXL TXD T QVXH T XHQX RXD (Out XHDV RXD (In) Valid Note and RI are set during S1P1 of the peripheral cycle ...
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AC Characteristics - SSLC: TWI Interface Timings Waveforms Figure 18. TWI Waveforms START or Repeated START condition SDA (INPUT/OUTPUT SCL (INPUT/OUTPUT) T ;STA HD AT/TSC8x251G2D 54 Table 47. TWI Interface AC Timing; V Symbol Parameter T ; STA ...
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AC Characteristics - SSLC: SPI Interface Definition of Symbols 4135D–8051–08/05 Table 48. SPI Interface Timing Symbol Definitions Signals C Clock I Data In O Data Out S SS# AT/TSC8x251G2D Conditions H High L Low V Valid X No Longer Valid ...
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Timings AT/TSC8x251G2D 56 Table 49. SPI Interface AC Timing; V Symbol Parameter T Clock Period CHCH T Clock High Time CHCX T Clock Low Time CLCX SS# Low to Clock edge SLCH SLCL Input ...
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Waveforms (1) SS# (output) SCK (SSCPOL = 0) (output) SCK (SSCPOL = 1) (output) MISO (input) MOSI Port Data (output) Note: 1. SS# handled by software. (1) SS# (output) SCK (SSCPOL = 0) (output) SCK (SSCPOL = 1) (output) MISO ...
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Figure 21. SPI Slave Waveforms (SSCPHA = 0) SS# (input) SCK (SSCPOL = 0) (input) SCK (SSCPOL = 1) (input) MISO (output) MOSI (input) Note: 1. Not Defined but generally the LSB of the character which has just been received. ...
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Timings Waveforms Figure 23. EPROM Programming Waveforms P1 = A15 A7 D7 EA#/VPP ALE/PROG# P0 4135D–8051–08/05 Table 51. EPROM Programming AC timings; V Symbol Parameter T XTAL1 Period OSC T ...
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Figure 24. EPROM Verifying Waveforms P1 = A15 A7 D7 Characteristics - External Clock Drive and Logic Level References Definition of Symbols Timings Waveforms AT/TSC8x251G2D 60 Address T AVQV T ELQV Mode = 28h, ...
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Figure 26. AC Testing Input/Output Waveforms INPUTS V - 0 0.45 V Note: For timing purposes, a port pin is no longer floating when a 100 mV change from load voltage occurs ...
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Absolute Maximum Rating and Operating Conditions Absolute Maximum Ratings Storage Temperature ......................................... -65 to +150°C Voltage on any other Pin to VSS ........................ -0 per I/O Pin ................................................................ Power Dissipation ........................................................... 1.5 W ...
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DC Characteristics High Speed Versions - Commercial & Industrial Table 55. DC Characteristics Symbol Parameter Input Low Voltage V IL (except EA#, SCL, SDA) Input Low Voltage (5) V IL1 (SCL, SDA) Input Low Voltage V IL2 (EA#) ...
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Notes: 1. Under steady-state (non-transient) conditions, I Maximum IOL per port pin Maximum IOL per 8-bit port:Port Ports 1 Maximum Total IOL for all: Output Pins IOL exceeds the test ...
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Low Voltage Versions - Commercial & Industrial Table 56. DC Characteristics Symbol Parameter Input Low Voltage V IL (except EA#, SCL, SDA) Input Low Voltage (5) V IL1 (SCL, SDA) Input Low Voltage V IL2 (EA#) Input high ...
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Maximum Total IOL for all:Output Pins71 mA If IOL exceeds the test conditions, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test conditions. 2. Capacitive loading on Ports 0 and 2 ...
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Figure 31. I Test Condition, Idle Mode DL (NC) Clock Signal All other pins are unconnected Figure 32. I Test Condition, Power-Down Mode PD RST (NC) XTAL2 XTAL1 VSS All other pins are unconnected AT/TSC8x251G2D VDD IDL RST VDD ...
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Packages List of Packages PDIL 40 - Mechanical Outline AT/TSC8x251G2D 68 • PDIL 40 • CDIL 40 with window • PLCC 44 • CQPJ 44 with window • VQFP 44 (10x10) Figure 33. Plastic Dual In Line Table 57. PDIL ...
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CDIL 40 with Window - Mechanical Outline 4135D–8051–08/05 Figure 34. Ceramic Dual In Line Table 58. CDIL Package Size Min 0.36 b2 1. 13.06 e 2.54 B.S.C. eA 15.24 B.S.C. L 3.18 ...
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PLCC 44 - Mechanical Outline AT/TSC8x251G2D 70 Figure 35. Plastic Lead Chip Carrier Table 59. PLCC Package Size Min A 4.20 A1 2.29 D 17.40 D1 16.44 D2 14.99 E 17.40 E1 16.44 E2 14.99 e 1.27 BSC G 1.07 ...
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CQPJ 44 with Window - Mechanical Outline 4135D–8051–08/05 Figure 36. Ceramic Quad Pack J Table 60. CQPJ Package Size Min 0. 17. 16.36 e 1.27 TYP f 0.43 J 0.86 Q ...
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VQFP 44 (10x10) - Mechanical Outline AT/TSC8x251G2D 72 Figure 37. Shrink Quad Flat Pack (Plastic) Table 61. VQFP Package Size Min 0.64 REF A2 0.64 REF A3 1.35 D 11.90 D1 9.90 E 11.90 E1 9.90 J ...
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Ordering Information AT/TSC80251G2D ROMless AT/TSC83251G2D 32 kilobytes MaskROM Note: 4135D–8051–08/05 Part Number High Speed Versions 4.5 to 5.5 V, Commercial and Industrial TSC80251G2D-16CB TSC80251G2D-24CB TSC80251G2D-24CE TSC80251G2D-24IA TSC80251G2D-24IB AT80251G2D-SLSUM AT80251G2D-3CSUM AT80251G2D-RLTUM Low Voltage Versions 2.7 to 5.5 V TSC80251G2D-L16CB TSC80251G2D-L16CE AT80251G2D-SLSUL ...
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... Low Voltage Versions 2.7 to 5.5 V TSC87251G2D-L16CB 32K OTPROM TSC87251G2D-L16CED 32K OTPROM AT87251G2D-SLSUL 32K OTPROM AT87251G2D-RLTUL 32K OTPROM Description 16 MHz, Commercial 0° to 70°C, PLCC 44 24 MHz, Commercial 0° to 70°C, PLCC 44 24 MHz, Commercial 0° to 70°C, VQFP 44 24 MHz, Industrial -40° to 85°C, PDIL 40 24 MHz, Industrial -40° ...
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Options • ROM code encryption (Please consult Atmel sales) • Tape & Reel or Dry Pack • Known good dice • Extended temperature range: -55°C to +125°C Product Markings 4135D–8051–08/05 ROMless versions Mask ROM versions ATMEL ATMEL Part number Customer ...
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