AT91SAM9260-QU ATMEL Corporation, AT91SAM9260-QU Datasheet - Page 398

• Manufacturer Part Number: AT91SAM9260-QU
• Manufacturer: ATMEL Corporation

Figure 31-18. TWI Read Operation with Single Data Byte and Internal Address
BEGIN
Set TWI clock
(CLDIV, CHDIV, CKDIV) in TWI_CWGR
(Needed only once)
Set the Control register:
- Master enable
TWI_CR = MSEN + SVDIS
Set the Master Mode register:
- Device slave address
- Internal address size (IADRSZ)
- Transfer direction bit
Read ==> bit MREAD = 1
Set the internal address
TWI_IADR = address
Start the transfer
TWI_CR = START | STOP
Read Status register
No
RXRDY = 1?
Yes
Read Receive Holding register
Read Status register
No
TXCOMP = 1?
Yes
END
AT91SAM9260
398
6221G–ATARM–31-Jan-08