PIC16F628A Microchip Technology Inc., PIC16F628A Datasheet

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PIC16F628A

Manufacturer Part Number
PIC16F628A
Description
Manufacturer
Microchip Technology Inc.
Datasheet

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PIC16F627A/628A/648A
Data Sheet
Flash-Based, 8-Bit CMOS
Microcontrollers with nanoWatt Technology
© 2007 Microchip Technology Inc.
DS40044F

Related parts for PIC16F628A

PIC16F628A Summary of contents

Page 1

... Microcontrollers with nanoWatt Technology © 2007 Microchip Technology Inc. PIC16F627A/628A/648A Flash-Based, 8-Bit CMOS Data Sheet DS40044F ...

Page 2

... EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified logo, microID, MPLAB, PIC DSCs ® code hopping devices, Serial EE OQ © 2007 Microchip Technology Inc. ® ...

Page 3

... Flash endurance - 1,000,000 write EEPROM endurance - 40 year data retention Program Memory Device Flash (words) PIC16F627A 1024 PIC16F628A 2048 PIC16F648A 4096 © 2007 Microchip Technology Inc. PIC16F627A/628A/648A Low-Power Features: • Standby Current: - 100 nA @ 2.0V, typical • Operating Current μ kHz, 2.0V, typical - 120 μ ...

Page 4

... RA0/AN0 RA7/OSC1/CLKIN 4 RA6/OSC2/CLKOUT RB7/T1OSI/PGD RB6/T1OSO/T1CKI/PGC 8 RB5 RB4/PGM 28-Pin QFN RA5/MCLR PIC16F627A/628A NC 4 PIC16F648A RB0/INT 7 21 RA7/OSC1/CLKIN 20 RA6/OSC2/CLKOUT RB7/T1OSI/PGD 15 RB6/T1OSO/T1CKI/PGC © 2007 Microchip Technology Inc. ...

Page 5

... When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. © 2007 Microchip Technology Inc. PIC16F627A/628A/648A DS40044F-page 3 ...

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... PIC16F627A/628A/648A NOTES: DS40044F-page 4 © 2007 Microchip Technology Inc. ...

Page 7

... The PIC16F627A/628A/648A family is supported by a full-featured macro assembler, a software simulator oscillator in-circuit emulator, a low cost in-circuit debugger, a low cost development programmer and a full-featured programmer. A Third Party “C” compiler support tool is also available. PIC16F628A PIC16F648A PIC16LF627A 20 20 2048 4096 1024 ...

Page 8

... PIC16F627A/628A/648A NOTES: DS40044F-page 6 © 2007 Microchip Technology Inc. ...

Page 9

... The serial numbers may be random, pseudo-random sequential. Serial programming allows each device to have a unique number, which can serve as an entry-code, password or ID number. © 2007 Microchip Technology Inc. PIC16F627A/628A/648A ® apply before or DS40044F-page 7 ...

Page 10

... PIC16F627A/628A/648A NOTES: DS40044F-page 8 © 2007 Microchip Technology Inc. ...

Page 11

... Table 3-1 lists device memory sizes (Flash, Data and EEPROM). TABLE 3-1: DEVICE MEMORY LIST Memory Device Flash RAM Program Data PIC16F627A 1024 x 14 224 x 8 PIC16F628A 2048 x 14 224 x 8 PIC16F648A 4096 x 14 256 x 8 PIC16LF627A 1024 x 14 224 x 8 PIC16LF628A 2048 x 14 224 x 8 PIC16LF648A ...

Page 12

... Oscillator ALU Power-on 8 Reset Watchdog W Reg Timer Brown-out Reset Low-Voltage Timer1 Timer2 USART Data EEPROM PORTA RA0/AN0 RA1/AN1 RA2/AN2/V REF RA3/AN3/CMP1 RA4/T0CK1/CMP2 RA5/MCLR/V PP RA6/OSC2/CLKOUT RA7/OSC1/CLKIN PORTB RB0/INT RB1/RX/DT RB2/TX/CK RB3/CCP1 RB4/PGM RB5 RB6/T1OSO/T1CKI/PGC RB7/T1OSI/PGD © 2007 Microchip Technology Inc. ...

Page 13

... RB1/RX/DT RB1 RX DT RB2/TX/CK RB2 TX CK RB3/CCP1 RB3 CCP1 Legend Output — = Not used TTL = TTL Input © 2007 Microchip Technology Inc. PIC16F627A/628A/648A Input Type Output Type ST CMOS Bidirectional I/O port AN — Analog comparator input ST CMOS Bidirectional I/O port AN — Analog comparator input ...

Page 14

... Timer1 oscillator input ST CMOS ICSP data I/O Power — Ground reference for logic and I/O pins Power — Positive supply for logic and I/O pins CMOS = CMOS Output I = Input OD = Open Drain Output Description P = Power ST = Schmitt Trigger Input AN = Analog © 2007 Microchip Technology Inc. ...

Page 15

... Note: All instructions are single cycle except for any program branches. These take two cycles since the fetch instruction is “flushed” from the pipeline while the new instruction is being fetched and then executed. © 2007 Microchip Technology Inc. PIC16F627A/628A/648A 3.2 Instruction Flow/Pipelining An instruction cycle consists of four Q cycles (Q1, Q2, Q3 and Q4) ...

Page 16

... PIC16F627A/628A/648A NOTES: DS40044F-page 14 © 2007 Microchip Technology Inc. ...

Page 17

... PIC16F628A and (0000h-0FFFh) for the PIC16F648A are physically implemented. Accessing a location above these boundaries will cause a wrap- around within the first space (PIC16F627A space (PIC16F628A space (PIC16F648A). The Reset vector is at 0000h and the interrupt vector is at 0004h (Figure 4-1). FIGURE 4-1: ...

Page 18

... PIC16F627A/628A/648A FIGURE 4-2: DATA MEMORY MAP OF THE PIC16F627A AND PIC16F628A (1) Indirect addr. Indirect addr. 00h TMR0 01h PCL 02h 03h STATUS FSR 04h PORTA 05h PORTB 06h 07h 08h 09h 0Ah PCLATH 0Bh INTCON PIR1 0Ch 0Dh 0Eh TMR1L TMR1H 0Fh 10h ...

Page 19

... CMCON 20h General Purpose Register 80 Bytes 6Fh 70h 16 Bytes 7Fh Bank 0 Unimplemented data memory locations, read as ‘0’. Note 1: Not a physical register. © 2007 Microchip Technology Inc. PIC16F627A/628A/648A (1) (1) Indirect addr. 80h TMR0 OPTION 81h PCL PCL 82h STATUS STATUS ...

Page 20

... T2CKPS1 T2CKPS0 -000 0000 52 — — — — 55 xxxx xxxx 55 xxxx xxxx CCP1M1 CCP1M0 55 --00 0000 OERR RX9D 72 0000 000x 77 0000 0000 80 0000 0000 — — — — — — — — CM1 CM0 61 0000 0000 © 2007 Microchip Technology Inc. ...

Page 21

... VRCON VREN VROE Legend Unimplemented locations read as ‘0’ unchanged unknown value depends on condition, shaded = unimplemented Note 1: For the initialization condition for registers tables, refer to Table 14-6 and Table 14-7. © 2007 Microchip Technology Inc. PIC16F627A/628A/648A Bit 5 Bit 4 Bit 3 Bit 2 T0CS T0SE PSA ...

Page 22

... Microchip Technology Inc. ...

Page 23

... Unimplemented Legend Unimplemented locations read as ‘0’ unchanged unknown value depends on condition, shaded = unimplemented Note 1: For the initialization condition for registers tables, refer to Table 14-6 and Table 14-7. © 2007 Microchip Technology Inc. PIC16F627A/628A/648A Bit 5 Bit 4 Bit 3 Bit 2 T0CS T0SE PSA ...

Page 24

... Digit Borrow out bit, respectively, in subtraction. See the SUBLW and SUBWF instructions for examples. R/W-0 R-1 R-1 RP1 RP0 Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared R/W-x R/W-x R/W bit Bit is unknown © 2007 Microchip Technology Inc. ...

Page 25

... Bit Value TMR0 Rate WDT Rate 000 001 010 011 100 101 110 111 Legend Readable bit -n = Value at POR © 2007 Microchip Technology Inc. PIC16F627A/628A/648A Note: To achieve a 1:1 prescaler assignment for TMR0, assign the prescaler to the WDT (PSA = 1). See Section 6.3.1 “Switching Prescaler Assignment”. R/W-1 R/W-1 R/W-1 T0CS T0SE ...

Page 26

... GIE (INTCON<7>). and R/W-0 R/W-0 R/W-0 T0IE INTE RBIE W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared R/W-0 R/W-0 R/W-x T0IF INTF RBIF bit Bit is unknown © 2007 Microchip Technology Inc. ...

Page 27

... Enables the TMR2 to PR2 match interrupt 0 = Disables the TMR2 to PR2 match interrupt bit 0 TMR1IE: TMR1 Overflow Interrupt Enable bit 1 = Enables the TMR1 overflow interrupt 0 = Disables the TMR1 overflow interrupt Legend Readable bit -n = Value at POR © 2007 Microchip Technology Inc. PIC16F627A/628A/648A R/W-0 R/W-0 U-0 RCIE TXIE — CCP1IE W = Writable bit U = Unimplemented bit, read as ‘ ...

Page 28

... R-0 R-0 U-0 R/W-0 RCIF TXIF — CCP1IF W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared © 2007 Microchip Technology Inc. R/W-0 R/W-0 TMR2IF TMR1IF bit Bit is unknown ...

Page 29

... No Brown-out Reset occurred Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs) Legend Readable bit -n = Value at POR © 2007 Microchip Technology Inc. PIC16F627A/628A/648A Note: BOR is unknown on Power-on Reset. It must then be set by the user and checked on subsequent Resets to see if BOR is cleared, indicating a brown-out has occurred. The BOR Status bit is a “ ...

Page 30

... Example 4-1. EXAMPLE 4-1: MOVLW MOVWF NEXT CLRF INCF BTFSS GOTO RETLW or a INDIRECT ADDRESSING 0x20 ;initialize pointer FSR ;to RAM INDF ;clear INDF register FSR ;inc pointer FSR,4 ;all done? NEXT ;no clear next ;yes continue © 2007 Microchip Technology Inc. ...

Page 31

... Register from opcode RP1 RP0 6 bank select location select 00h RAM File Registers 7Fh Bank 0 Note: For memory map detail see Figure 4-3, Figure 4-2 and Figure 4-1. © 2007 Microchip Technology Inc. PIC16F627A/628A/648A Status Register 0 IRP bank select 180h Bank 1 Bank 2 ...

Page 32

... PIC16F627A/628A/648A NOTES: DS40044F-page 30 © 2007 Microchip Technology Inc. ...

Page 33

... When in this mode, the V very high-impedance output. The user must configure TRISA<2> bit as an input and use high-impedance loads. © 2007 Microchip Technology Inc. PIC16F627A/628A/648A In one of the comparator modes defined by the CMCON register, pins RA3 and RA4 become outputs of the comparators. The TRISA< ...

Page 34

... CK Q Data Latch TRISA CK Q TRIS Latch RD TRISA RD PORTA To Comparator DS40044F-page 32 PIN V DD RA2 Pin V SS (CMCON Reg.) Comparator Mode = 110 RA3 Pin Analog V Input Mode SS (CMCON Reg.) Schmitt Trigger Input Buffer D © 2007 Microchip Technology Inc. ...

Page 35

... MCLRE MCLR circuit MCLR Filter Schmitt Trigger Program Input Buffer mode HV Detect Data Bus RD V TRISA PORTA © 2007 Microchip Technology Inc. PIC16F627A/628A/648A Comparator Mode = 110 (CMCON Reg FIGURE 5-6: PIN PP From OSC1 CLKOUT(F OSC D WR PORTA OSC ...

Page 36

... To Clock Circuits Data Bus PORTA CK Q Data Latch TRISA CK Q TRIS Latch RD TRISA ( 100, 101 OSC RD PORTA Note 1: INTOSC with CLKOUT and INTOSC with I/O. DS40044F-page Schmitt Trigger Input Buffer RA7/OSC1/CLKIN Pin V SS © 2007 Microchip Technology Inc. ...

Page 37

... VRCON VREN VROE Legend Unimplemented locations read as ‘0’ unchanged unknown value depends on condition. Shaded cells are not used for PORTA. Note 1: MCLRE configuration bit sets RA5 functionality. © 2007 Microchip Technology Inc. PIC16F627A/628A/648A Output Type ST CMOS Bidirectional I/O port AN — ...

Page 38

... FIGURE 5-8: BLOCK DIAGRAM OF RB0/INT PIN RBPU Data Bus PORTB CK Q Data Latch TRISB CK Q TRIS Latch TTL RD TRISB Input Buffer PORTB INT Schmitt Trigger © 2007 Microchip Technology Inc Weak Pull- RB0/INT V SS ...

Page 39

... Peripheral OE TTL Input RD TRISB Buffer PORTB USART Receive Input Schmitt Trigger Note 1: Peripheral OE (output enable) is only active if peripheral select is active. © 2007 Microchip Technology Inc. PIC16F627A/628A/648A FIGURE 5-10 Weak RBPU Pull-up P SPEN V DD USART TX/CK Output Data Bus RB1/ RX/DT WR PORTB ...

Page 40

... Data Latch TRISB CK Q TRIS Latch (2) Peripheral OE RD TRISB PORTB CCP In Schmitt Trigger Note 1: Peripheral OE (output enable) is only active if peripheral select is active. DS40044F-page Weak Pull- RB3/ CCP1 V SS TTL Input Buffer © 2007 Microchip Technology Inc. ...

Page 41

... WR TRISB CK TRIS Latch RD TRISB LVP (Configuration Bit) RD PORTB PGM input Set RBIF From other RB<7:4> pins Note: The low-voltage programming disables the interrupt-on-change and the weak pull-ups on RB4. © 2007 Microchip Technology Inc. PIC16F627A/628A/648A Schmitt Trigger weak pull-up ...

Page 42

... BLOCK DIAGRAM OF RB5 PIN RBPU Data Bus PORTB CK Q Data Latch TRISB CK Q TRIS Latch RD TRISB RD PORTB Set RBIF From other RB<7:4> pins DS40044F-page weak P pull- TTL input buffer © 2007 Microchip Technology Inc. RB5 pin ...

Page 43

... FIGURE 5-14: BLOCK DIAGRAM OF RB6/T1OSO/T1CKI/PGC PIN RBPU Data Bus WR PORTB WR TRISB TRIS Latch RD TRISB T1OSCEN RD PORTB TMR1 Clock From RB7 Serial Programming Clock Set RBIF © 2007 Microchip Technology Inc. PIC16F627A/628A/648A Data Latch Schmitt Trigger From other RB<7:4> pins ...

Page 44

... T10SCEN RD PORTB Serial Programming Input Set RBIF DS40044F-page Data Latch TRIS Latch Q From other Q RB<7:4> pins weak pull-up P TMR1 oscillator V DD RB7/T1OSI/ PGD pin V SS TTL input buffer Schmitt Trigger © 2007 Microchip Technology Inc. ...

Page 45

... OPTION RBPU INTEDG Legend unchanged unknown. Shaded cells are not used for PORTB. Note 1: LVP configuration bit sets RB4 functionality. © 2007 Microchip Technology Inc. PIC16F627A/628A/648A Output Type TTL CMOS Bidirectional I/O port. Can be software programmed for internal weak pull-up. ...

Page 46

... T ) where T = instruction cycle and READ-MODIFY-WRITE INSTRUCTIONS ON AN I/O PORT PORTB<3:0> Outputs PORT latchPORT Pins ---------- ---------- ; ;01pp pppp 11pp pppp ; ;10pp pppp 11pp pppp ;10pp pppp 10pp pppp NOP Execute NOP = propagation delay of Q1 cycle PD © 2007 Microchip Technology Inc. ...

Page 47

... Timer0 module interrupt service routine before re- enabling this interrupt. The Timer0 interrupt cannot wake the processor from Sleep since the timer is shut off during Sleep. © 2007 Microchip Technology Inc. PIC16F627A/628A/648A 6.2 Using Timer0 with External Clock When an external clock input is used for Timer0, it must meet certain requirements ...

Page 48

... WDT, a CLRWDT instruction will clear the prescaler along with the Watchdog Timer. The prescaler is not readable or writable SYNC 1 2 Cycles 0 T0CS PSA WDT Postscaler/ TMR0 Prescaler 8 8-to-1MUX PS<2:0> 1 WDT Time-out 0 PSA Data Bus 8 TMR0 Reg Set flag bit T0IF on Overflow © 2007 Microchip Technology Inc. ...

Page 49

... Legend Unimplemented locations, read as ‘0’ unchanged unknown. Shaded cells are not used for Timer0. Note 1: Option is referred by OPTION_REG in MPLAB © 2007 Microchip Technology Inc. PIC16F627A/628A/648A To change prescaler from the WDT to the Timer0 module, use the sequence shown in Example 6-2. This precaution must be taken even if the WDT is disabled. ...

Page 50

... That is, the TRISB<7:6> value is ignored. U-0 R/W-0 R/W-0 R/W-0 — T1CKPS1 T1CKPS0 T1OSCEN (1) /4) OSC W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared (CCP) Module”). and RB6/T1OSO/T1CKI/PGC pins R/W-0 R/W-0 R/W-0 T1SYNC TMR1CS TMR1ON bit Bit is unknown © 2007 Microchip Technology Inc. ...

Page 51

... TMR1 TMR1H T1OSC RB6/T1OSO/T1CKI/PGC RB7/T1OSI/PGD Note 1: When the T1OSCEN bit is cleared, the inverter and feedback resistor are turned off. This eliminates power drain. © 2007 Microchip Technology Inc. PIC16F627A/628A/648A 7.2.1 EXTERNAL CLOCK INPUT TIMING FOR SYNCHRONIZED COUNTER MODE When an external clock input is used for Timer1 in Synchronized Counter mode, it must meet certain requirements ...

Page 52

... Reading ; the high and low bytes now will read a good ; value. ; MOVF TMR1H, W ;Read high byte MOVWF TMPH ; MOVF TMR1L, W ;Read low byte MOVWF TMPL ; ; Re-enable the Interrupts (if required) CONTINUE ;Continue with your ;code © 2007 Microchip Technology Inc. ...

Page 53

... T1CON — — T1CKPS1 Legend unknown unchanged unimplemented read as ‘0’. Shaded cells are not used by the Timer1 module. © 2007 Microchip Technology Inc. PIC16F627A/628A/648A 7.5 Resetting Timer1 Using a CCP Trigger Output If the CCP1 module is configured in Compare mode to generate a “special event trigger” (CCP1M<3:0> = 1011), this signal will reset Timer1 ...

Page 54

... The TMR2 output (before the postscaler) is fed to the Synchronous Serial Port module which optionally uses it to generate shift clock. FIGURE 8-1: TIMER2 BLOCK DIAGRAM Sets flag TMR2 bit TMR2IF output Reset Prescaler TMR2 Reg 1:1, 1:4, 1:16 Postscaler Comparator 1:1 to 1:16 EQ T2CKPS<1:0> 4 PR2 Reg TOUTPS<3:0> © 2007 Microchip Technology Inc OSC 2 ...

Page 55

... T2CON — 92h PR2 Timer2 Period Register Legend unknown unchanged unimplemented read as ‘0’. Shaded cells are not used by the Timer2 module. © 2007 Microchip Technology Inc. PIC16F627A/628A/648A R/W-0 R/W-0 R/W-0 TOUTPS0 W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘ ...

Page 56

... PIC16F627A/628A/648A NOTES: DS40044F-page 54 © 2007 Microchip Technology Inc. ...

Page 57

... Compare mode, generate software interrupt on match (CCP1IF bit is set, CCP1 pin is unaffected) 1011 = Compare mode, trigger special event (CCP1IF bit is set; CCP1 resets TMR1 11xx = PWM mode Legend Readable bit -n = Value at POR © 2007 Microchip Technology Inc. PIC16F627A/628A/648A TABLE 9-1: CCP Mode Capture Compare PWM ...

Page 58

... CCP module off ; the new prescaler ; mode value and CCP ON ;Load CCP1CON with this ; value COMPARE MODE OPERATION BLOCK DIAGRAM Set flag bit CCP1IF (PIR1<2>) CCPR1H CCPR1L Output Comparator Logic match TMR1H TMR1L CCP1CON<3:0> Mode Select © 2007 Microchip Technology Inc. ...

Page 59

... CCP1CON — — CCP1X Legend unknown unchanged unimplemented read as ‘0’. Shaded cells are not used by Capture and Timer1. © 2007 Microchip Technology Inc. PIC16F627A/628A/648A 9.2.4 SPECIAL EVENT TRIGGER In this mode (CCP1M<3:0>=1011), an internal hard- ware trigger is generated, which may be used to initiate an action ...

Page 60

... Module”) is not used in the determination of the PWM frequency. The postscaler could be used to have a servo update rate at a different frequency than the PWM output. PWM OUTPUT Period TMR2 = PR2 TMR2 = Duty Cycle [ ( ) ] 4 ⋅ ⋅ ⋅ = PR2 + 1 Tosc TMR2 prescale value © 2007 Microchip Technology Inc. ...

Page 61

... Capture/Compare/PWM Register 1 (MSB) 17h CCP1CON — — Legend unknown unchanged unimplemented read as ‘0’. Shaded cells are not used by PWM and Timer2. © 2007 Microchip Technology Inc. PIC16F627A/628A/648A Maximum PWM resolution (bits) for a given PWM frequency: PWM Resolution Note: If the PWM duty cycle value is longer than the PWM period the CCP1 pin will not be cleared ...

Page 62

... PIC16F627A/628A/648A NOTES: DS40044F-page 60 © 2007 Microchip Technology Inc. ...

Page 63

... CM<2:0>: Comparator Mode bits Figure 10-1 shows the comparator modes and CM<2:0> bit settings Legend Readable bit -n = Value at POR © 2007 Microchip Technology Inc. PIC16F627A/628A/648A The CMCON register, shown in Register 10-1, controls the comparator input and output multiplexers. A block two analog diagram of the comparator is shown in Figure 10-1. ...

Page 64

... CIS = CIS = 1 C1V OUT CIS = 0 IN CIS = 1 C2V OUT From V REF Module C1V C1 OUT C2V C2 OUT CIS = CIS = 1 C1V OUT C2V OUT © 2007 Microchip Technology Inc. ...

Page 65

... Comparator Reference An external or internal reference signal may be used depending on the comparator Operating mode. The analog signal that is present compared to the IN signal and the digital output of the comparator IN is adjusted accordingly (Figure 10-2). © 2007 Microchip Technology Inc. PIC16F627A/628A/648A FIGURE 10- ...

Page 66

... FIGURE 10-3: MODIFIED COMPARATOR OUTPUT BLOCK DIAGRAM CnI NV To RA3/AN3/CMP1 or RA4/T0CK1/CMP2 pin To Data Bus CMCON<7:6> RD CMCON Set CMIF bit From other Comparator DS40044F-page 64 The Reset © 2007 Microchip Technology Inc. CnV OUT Q3 Q1 ...

Page 67

... Clear flag bit CMIF. A mismatch condition will continue to set flag bit CMIF. Reading CMCON will end the mismatch condition and allow flag bit CMIF to be cleared. © 2007 Microchip Technology Inc. PIC16F627A/628A/648A 10.7 Comparator Operation During Sleep When a comparator is active and the device is placed in Sleep mode, the comparator remains active and the interrupt is functional if enabled ...

Page 68

... CCP1IF TMR2IF TMR1IF 0000 -000 0000 -000 RCIE TXIE — CCP1IE TMR2IE TMR1IE 0000 -000 0000 -000 R IC Value on Value on Bit 0 All Other POR Resets CM0 0000 0000 0000 0000 RBIF 0000 000x 0000 000u © 2007 Microchip Technology Inc. ...

Page 69

... VR<3:0>: V REF When VRR = 1: V When VRR = 0: V Legend Readable bit -n = Value at POR © 2007 Microchip Technology Inc. PIC16F627A/628A/648A The equations used to calculate the output of the Voltage Reference module are as follows: if VRR = 1: if VRR = 0: V REF The setting time of the Voltage Reference module must be considered when changing the V (Table 17-3) ...

Page 70

... Due to the limited drive capability, a buffer must be used in conjunction with the Voltage Reference module output for external connec- tions to V REF technique derived and DD REF R 8R VRR (From VRCON<3:0> Figure 11-2 shows an example buffering © 2007 Microchip Technology Inc. ...

Page 71

... VRCON VREN VROE 1Fh CMCON C2OUT C1OUT 85h TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 1111 1111 1111 1111 Legend Unimplemented, read as ‘0’. © 2007 Microchip Technology Inc. PIC16F627A/628A/648A Op Amp RA2 + Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 VRR — ...

Page 72

... PIC16F627A/628A/648A NOTES: DS40044F-page 70 © 2007 Microchip Technology Inc. ...

Page 73

... TX9D: 9th bit of transmit data. Can be parity bit. Note 1: SREN/CREN overrides TXEN in SYNC mode. Legend Readable bit -n = Value at POR © 2007 Microchip Technology Inc. PIC16F627A/628A/648A The USART can be configured in the following modes: • Asynchronous (full-duplex) • Synchronous • Synchronous Bit SPEN (RCSTA<7>) and bits TRISB<2:1> have to be ...

Page 74

... RX9D: 9th bit of received data (Can be parity bit) Legend Readable bit -n = Value at POR DS40044F-page 72 R/W-0 R/W-0 R/W-0 RX9 SREN CREN ADEN W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared R-0 R-0 R-x FERR OERR RX9D bit Bit is unknown © 2007 Microchip Technology Inc. ...

Page 75

... RX9 99h SPBRG Baud Rate Generator Register Legend unknown unimplemented read as ‘0’. Shaded cells are not used for the BRG. © 2007 Microchip Technology Inc. PIC16F627A/628A/648A EQUATION 12-1: Desired Baud Rate Calculated Baud Rate , the nearest (Calculated Baud Rate - Desired Baud Rate) ...

Page 76

... SPBRG value KBAUD ERROR (decimal) 0.303 +1.14% 26 1.170 -2.48 — — NA — — NA — — NA — — NA — — NA — — NA — — 8.192 — 0 0.032 — 255 © 2007 Microchip Technology Inc. ...

Page 77

... NA — — 300 NA — 500 NA — HIGH 55.93 — LOW 0.2185 — © 2007 Microchip Technology Inc. PIC16F627A/628A/648A 16 MHz SPBRG value value KBAUD ERROR (decimal) — NA — — 255 1.202 +0.16% 207 129 2.404 +0.16% 103 32 9.615 +0.16 19.23 +0.16 83.33 +8.51% ...

Page 78

... NA — — NA — — 32.768 kHz SPBRG value KBAUD ERROR (decimal © 2007 Microchip Technology Inc. ...

Page 79

... Note 1: The TSR register is not mapped in data memory not available to the user. 2: Flag bit TXIF is set when enable bit TXEN is set. © 2007 Microchip Technology Inc. PIC16F627A/628A/648A Transmission is enabled by setting enable bit TXEN (TXSTA<5>). The actual transmission will not occur ...

Page 80

... Transmit Shift Reg. (Transmit shift reg. empty flag) DS40044F-page 78 Data Bus TXREG register 8 MSb LSb (8) ² ² ² 0 TSR register TRMT TX9 TX9D bit 0 bit 1 Word 1 Pin Buffer and Control RB2/TX/CK pin SPEN bit 7/8 Stop bit © 2007 Microchip Technology Inc. ...

Page 81

... CMIE 98h TXSTA CSRC TX9 99h SPBRG Baud Rate Generator Register Legend unknown unimplemented locations read as ‘0’. Shaded cells are not used for Asynchronous Transmission. © 2007 Microchip Technology Inc. PIC16F627A/628A/648A bit 0 bit 1 Word 1 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 RCIF TXIF — ...

Page 82

... OERR CREN ÷ 64 RSR register MSb or ÷ Stop (8) Data RX9 Recovery Enable Load of Receive Buffer RX9D RCREG register RCREG register RX9D RCIF Interrupt RCIE FERR LSb • • • Start 8 8 FIFO 8 Data Bus © 2007 Microchip Technology Inc. ...

Page 83

... This timing diagram shows an address byte followed by an data byte. The data byte is read into the RCREG (Receive Buffer) because ADEN was updated after an address match, and was cleared to a ‘0’, so the contents of the Receive Shift Register (RSR) are read into the Receive Buffer regardless of the value of bit 8. © 2007 Microchip Technology Inc. PIC16F627A/628A/648A Start ...

Page 84

... CCP1IE TMR2IE TMR1IE 0000 -000 0000 -000 TXEN SYNC — BRGH TRMT Value on Value on Bit 0 all other POR Resets RX9D 0000 000x 0000 000x 0000 0000 0000 0000 TX9D 0000 -010 0000 -010 0000 0000 0000 0000 © 2007 Microchip Technology Inc. ...

Page 85

... SPBRG Baud Rate Generator Register Legend unknown unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous reception. © 2007 Microchip Technology Inc. PIC16F627A/628A/648A The ADEN bit will only take effect when the receiver is configured in 9-bit mode (RX9 = 1). When ADEN is disabled (= 0), all data bytes are received and the 9th bit can be used as the parity bit ...

Page 86

... If interrupts are desired, then set enable bit TXIE 9-bit transmission is desired, then set bit TX9. 6. Enable the transmission by setting bit TXEN 9-bit transmission is selected, the ninth bit should be loaded in bit TX9D. 8. Start each transmission by loading data to the TXREG register. © 2007 Microchip Technology Inc. ...

Page 87

... Sync Master Mode; SPBRG = 0. Continuous transmission of two 8-bit words. FIGURE 12-9: SYNCHRONOUS TRANSMISSION (THROUGH TXEN) RB1/RX/DT pin RB2/TX/CK pin Write to TXREG Reg TXIF bit TRMT bit TXEN bit © 2007 Microchip Technology Inc. PIC16F627A/628A/648A Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 TXIF — CCP1IF TMR2IF TMR1IF 0000 -000 ...

Page 88

... CCP1IE TMR2IE TMR1IE -000 0000 — BRGH TRMT Value on: Value on all Bit 0 POR other Resets 0000 -000 RX9D 0000 000x 0000 000x 0000 0000 0000 0000 -000 -000 TX9D 0000 -010 0000 -010 0000 0000 0000 0000 © 2007 Microchip Technology Inc. ...

Page 89

... If enable bit TXIE is set, the interrupt will wake the chip from Sleep and if the global interrupt is enabled, the program will branch to the interrupt vector (0004h). © 2007 Microchip Technology Inc. PIC16F627A/628A/648A bit 2 bit 3 bit 4 bit 5 Follow these steps when setting up a Synchronous Slave Transmission: 1 ...

Page 90

... Value on Value on all Bit 0 POR other Resets 0000 -000 RX9D 0000 000x 0000 000x 0000 0000 0000 0000 0000 -000 TX9D 0000 -010 0000 -010 0000 0000 0000 0000 © 2007 Microchip Technology Inc. ...

Page 91

... EEADR: Specifies one of 128 locations of EEPROM Read/Write Operation Legend Readable bit -n = Value at POR © 2007 Microchip Technology Inc. PIC16F627A/628A/648A The EEPROM data memory allows byte read and write. A byte write automatically erases the location and writes the new data (erase before write). The EEPROM data memory is rated for high erase/write cycles ...

Page 92

... The EECON2 register is used exclusively in the data EEPROM write sequence. U-0 U-0 U-0 R/W-x — — — WRERR W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared R/W-0 R/S-0 R/S-0 WREN WR RD bit Bit is unknown © 2007 Microchip Technology Inc. ...

Page 93

... After a write sequence has been initiated, clearing the WREN bit will not affect this write cycle. The WR bit will be inhibited from being set unless the WREN bit is set. © 2007 Microchip Technology Inc. PIC16F627A/628A/648A At the completion of the write cycle, the WR bit is cleared in hardware and the EE Write Complete Interrupt Flag bit (EEIF) is set ...

Page 94

... EE writes ;enable interrupts (optional) © 2007 Microchip Technology Inc. ...

Page 95

... EECON2 EEPROM Control Register 2 Legend unknown unchanged unimplemented read as ‘0’ value depends upon condition. Shaded cells are not used by data EEPROM. Note 1: EECON2 is not a physical register. © 2007 Microchip Technology Inc. PIC16F627A/628A/648A Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 — — ...

Page 96

... PIC16F627A/628A/648A NOTES: DS40044F-page 94 © 2007 Microchip Technology Inc. ...

Page 97

... The RC oscillator option saves system cost while the LP crystal option saves power. A set of configuration bits are used to select various options. © 2007 Microchip Technology Inc. PIC16F627A/628A/648A 14.1 Configuration Bits The configuration bits can be programmed (read as ‘0’) or left unprogrammed (read as ‘ ...

Page 98

... CP: Flash Program Memory Code Protection bit (PIC16F648A Code protection off 0 = 0000h to 0FFFh code-protected (PIC16F628A Code protection off 0 = 0000h to 07FFh code-protected (PIC16F627A Code protection off 0 = 0000h to 03FFh code-protected bit 12-9: Unimplemented: Read as ‘0’ (3) bit 8: CPD: Data Code Protection bit ...

Page 99

... RS (2) C2 PIC16F627A/628A/648A Note 1: A series resistor may be required for AT strip cut crystals. 2: See Table 14-1 and Table 14-2 for recommended values of C1 and C2. © 2007 Microchip Technology Inc. PIC16F627A/628A/648A TABLE 14-1: Mode XT 455 kHz 2.0 MHz 4.0 MHz HS 8.0 MHz 16.0 MHz Note: Higher capacitance increases the stability of the oscillator, but also increases the start-up time ...

Page 100

... AC/DC timing requirements listed in Section 17.6 “Timing Diagrams and Specifications”. Figure 14-4 below shows how an external clock circuit should be configured. FIGURE 14-4: EXTERNAL CLOCK INPUT OPERATION (EC, HS OSC CONFIGURATION) Clock from RA7/OSC1/CLKIN ext. system PIC16F627A/628A/648A RA6 RA6/OSC2/CLKOUT © 2007 Microchip Technology Inc. CLKIN PIC16F627A/ 628A/648A Z ...

Page 101

... The PIC16F627A/628A/648A can be configured to provide a clock out signal by programming the Configuration Word. The oscillator frequency, divided by 4 can be used for test purposes or to synchronize other logic. © 2007 Microchip Technology Inc. PIC16F627A/628A/648A 14.2.8 SPECIAL FEATURE: DUAL-SPEED OSCILLATOR MODES A software programmable dual-speed oscillator mode is provided when the PIC16F627A/628A/648A is configured in the INTOSC oscillator mode ...

Page 102

... BOREN OST/PWRT OST 10-bit Ripple-counter OSC1/ CLKIN Pin PWRT (1) On-chip 10-bit Ripple-counter OSC Note 1: This is a separate oscillator from the INTOSC/RC oscillator. DS40044F-page 100 See Table 14-3 for time out situations. Enable PWRT Enable OST © 2007 Microchip Technology Inc Chip_Reset R Q ...

Page 103

... Reset V DD Internal Reset Note delay only if PWRTE bit is programmed to ‘0’. © 2007 Microchip Technology Inc. PIC16F627A/628A/648A 14.4.3 OSCILLATOR START-UP TIMER (OST) The OST provides a 1024 oscillator cycle (from OSC1 input) delay after the PWRT delay is over. Program execution will not start until the OST time out is complete ...

Page 104

... Illegal set on POR Illegal set on POR Brown-out Reset WDT Reset WDT Wake-up MCLR Reset during normal operation MCLR Reset during Sleep may have DD Wake-up from Sleep PWRTE = 1 1024•T 1024•T OSC OSC — — 6 μs — © 2007 Microchip Technology Inc. ...

Page 105

... Legend unchanged unknown unimplemented bit, reads as ‘0’. Note 1: When the wake-up is due to an interrupt and global enable bit, GIE is set, the PC is loaded with the interrupt vector (0004h) after execution © 2007 Microchip Technology Inc. PIC16F627A/628A/648A Bit 5 Bit 4 Bit 3 ...

Page 106

... Microchip Technology Inc. ...

Page 107

... Internal POR PWRT Time Out OST Time Out Internal Reset FIGURE 14-10: TIME OUT SEQUENCE ON POWER-UP (MCLR TIED MCLR Internal POR PWRT Time Out OST Time Out Internal Reset © 2007 Microchip Technology Inc. PIC16F627A/628A/648A T PWRT T OST T PWRT T OST DD T PWRT ...

Page 108

... Internal Brown-out Reset should be disabled when using this circuit. 3: Resistors should be adjusted for the characteristics of the transistor. pin break- DD EXTERNAL BROWN-OUT PROTECTION CIRCUIT MCLR 40k PIC16F627A/628A/648A is below a certain level such that 0 0 © 2007 Microchip Technology Inc. ...

Page 109

... Note 1: Some peripherals depend upon the system clock for operation. Since the system clock is suspended during Sleep, only those peripherals which do not depend upon the system clock will wake the part from Sleep. See Section 14.8.1 “Wake-up from Sleep”. © 2007 Microchip Technology Inc. PIC16F627A/628A/648A When an interrupt is responded to, the GIE is cleared to disable any further interrupt, the return address is pushed into the stack and the PC is loaded with 0004h ...

Page 110

... Interrupt Latency ( Inst ( — Dummy Cycle Inst (PC) . Synchronous latency = where “Comparator Interrupts” for 0004h 0005h Inst (0004h) Inst (0005h) Inst (0004h) Dummy Cycle = instruction cycle time. CY © 2007 Microchip Technology Inc. ...

Page 111

... STATUS_TEMP,W;swap STATUS_TEMP register ;into W, sets bank to original ;state MOVWF STATUS ;move W into STATUS ;register SWAPF W_TEMP,F ;swap W_TEMP SWAPF W_TEMP,W ;swap W_TEMP into W © 2007 Microchip Technology Inc. PIC16F627A/628A/648A Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 T0IE INTE RBIE T0IF INTF RCIF TXIF — ...

Page 112

... PS<2:0> TMR0 (Figure 6-1) PSA Value on Value on Bit 0 all other POR Reset Resets FOSC0 uuuu uuuu uuuu uuuu PS0 1111 1111 1111 1111 or V with no external DD SS should be disabled. I/O pins REF DD lowest current consumption. The ). IHMC © 2007 Microchip Technology Inc. ...

Page 113

... CPD bits by turning off the code protection. The entire data EEPROM and Flash program memory will be erased to turn the code protection off. © 2007 Microchip Technology Inc. PIC16F627A/628A/648A When the SLEEP instruction is being executed, the next instruction ( pre-fetched. For the device to wake-up through an interrupt event, the corresponding interrupt enable bit must be set (enabled) ...

Page 114

... It should be noted, that once the LVP bit is programmed to ‘0’, only High-Voltage Programming mode can be used to program the device. PP This mode allows the on the MCLR pin. IHH must be 5.0V +10% during erase on MCLR. The LVP bit IHH © 2007 Microchip Technology Inc. ...

Page 115

... TABLE 14-19: DEBUGGER RESOURCES I/O pins ICDCLK, ICDDATA Stack 1 level Program Memory Address 0h must be NOP 300h-3FEh The PIC16F648A-ICD device with header is supplied as an assembly. See Microchip Part Number AC162053. © 2007 Microchip Technology Inc. PIC16F627A/628A/648A DS40044F-page 113 ...

Page 116

... PIC16F627A/628A/648A NOTES: DS40044F-page 114 © 2007 Microchip Technology Inc. ...

Page 117

... Destination select store result store result in file register f. Default Time-out bit PD Power-down bit © 2007 Microchip Technology Inc. PIC16F627A/628A/648A The instruction set is highly orthogonal and is grouped into three basic categories: • Byte-oriented operations • Bit-oriented operations • Literal and control operations ...

Page 118

... TO,PD 0000 0110 0100 1kkk kkkk kkkk Z 1000 kkkk kkkk 00xx kkkk kkkk 0000 0000 1001 01xx kkkk kkkk 0000 0000 1000 TO,PD 0000 0110 0011 C,DC,Z 110x kkkk kkkk Z 1010 kkkk kkkk © 2007 Microchip Technology Inc. ...

Page 119

... Cycles: 1 Example ADDWF REG1, 0 Before Instruction W = 0x17 REG1 = 0xC2 After Instruction W = 0xD9 REG1 = 0xC2 © 2007 Microchip Technology Inc. PIC16F627A/628A/648A ANDLW k Syntax: Operands: Operation: Status Affected: kkkk kkkk Encoding: Description: Words: Cycles: Example ANDWF Syntax: f,d Operands: Operation: Status Affected: ...

Page 120

... NOP is executed instead, making this a two-cycle instruction. 1 1(2) HERE BTFSC REG1 FALSE GOTO PROCESS_CODE TRUE • • • Before Instruction PC = address HERE After Instruction if REG<1> address TRUE if REG<1> = address FALSE © 2007 Microchip Technology Inc. ...

Page 121

... FALSE GOTO TRUE • • • Before Instruction PC = address HERE After Instruction if FLAG<1> address FALSE if FLAG<1> address TRUE © 2007 Microchip Technology Inc. PIC16F627A/628A/648A CALL Syntax: Operands: Operation: Status Affected: bfff ffff Encoding: Description: Words: Cycles: REG1 PROCESS_CODE Example ...

Page 122

... Decrement register ‘f’. If ‘d’ is ‘0’. the result is stored in the W register. If ‘d’ is ‘1’, the result is stored back in register ‘f’ DECF CNT, 1 Before Instruction CNT = 0x01 After Instruction CNT = 0x00 © 2007 Microchip Technology Inc. ...

Page 123

... Before Instruction PC = address After Instruction REG1 = REG1 - 1 if REG1 = address CONTINUE if REG1 ≠ address HERE+1 © 2007 Microchip Technology Inc. PIC16F627A/628A/648A GOTO Syntax: Operands: Operation: skip if result = Status Affected: Encoding: dfff ffff Description: Words: Cycles: Example REG1, 1 ...

Page 124

... A NOP is executed instead making it a two-cycle instruction. 1 1(2) HERE INCFSZ REG1, 1 GOTO LOOP CONTINUE • • • Before Instruction PC = address HERE After Instruction REG1 = REG1 + 1 if CNT = address CONTINUE if REG1≠ address HERE +1 © 2007 Microchip Technology Inc. ...

Page 125

... Words: 1 Cycles: 1 Example IORWF REG1, 0 Before Instruction REG1 = 0x13 W = 0x91 After Instruction REG1 = 0x13 W = 0x93 © 2007 Microchip Technology Inc. PIC16F627A/628A/648A MOVLW Syntax: Operands: Operation: Status Affected: Encoding: kkkk kkkk Description: Words: Cycles: Example MOVF f,d Syntax: Operands: ...

Page 126

... None 00 0000 0000 1001 Return from Interrupt. Stack is POPed and Top-of-Stack (TOS) is loaded in the PC. Interrupts are enabled by setting Global Interrupt Enable bit, GIE (INTCON<7>). This is a two- cycle instruction RETFIE After Interrupt PC = TOS GIE = 1 © 2007 Microchip Technology Inc. ...

Page 127

... POPed and the top of the stack (TOS) is loaded into the program counter. This is a two-cycle instruction. Words: 1 Cycles: 2 Example RETURN After Interrupt PC = TOS © 2007 Microchip Technology Inc. PIC16F627A/628A/648A RLF Syntax: Operands: Operation: Status Affected: Encoding: kkkk kkkk Description: Words: ...

Page 128

... The result is placed in the W register SUBLW 0x02 Before Instruction After Instruction result is positive Before Instruction After Instruction result is zero Before Instruction After Instruction W = 0xFF result is negative © 2007 Microchip Technology Inc. ...

Page 129

... Example 3: Before Instruction REG1 = After Instruction REG1 = 0xFF result is negative © 2007 Microchip Technology Inc. PIC16F627A/628A/648A SWAPF Syntax: Operands: Operation: Status Affected: Encoding: dfff ffff Description: Words: Cycles: Example TRIS Syntax: Operands: Operation: ...

Page 130

... W register with register ‘f’. If ‘d’ is ‘0’, the result is stored in the W register. If ‘d’ is ‘1’, the result is stored back in register ‘f’ XORWF REG1, 1 Before Instruction REG1 = 0xAF W = 0xB5 After Instruction REG1 = 0x1A W = 0xB5 © 2007 Microchip Technology Inc. ...

Page 131

... PICSTART Plus Development Programmer - MPLAB PM3 Device Programmer - PICkit™ 2 Development Programmer • Low-Cost Demonstration and Development Boards and Evaluation Kits © 2007 Microchip Technology Inc. PIC16F627A/628A/648A 16.1 MPLAB Integrated Development Environment Software The MPLAB IDE software brings an ease of software development previously unseen in the 8/16-bit micro- controller market ...

Page 132

... MPLAB C30 C Compilers, and the MPASM and MPLAB ASM30 Assemblers. The software simulator offers the flexibility to develop and debug code outside of the hardware laboratory environment, making it an excellent, economical software development tool. ® DSCs on an instruction © 2007 Microchip Technology Inc. ...

Page 133

... Microchip Technology Inc. PIC16F627A/628A/648A 16.9 MPLAB ICD 2 In-Circuit Debugger Microchip’s In-Circuit Debugger, MPLAB ICD ...

Page 134

... SEEVAL evaluation system, Sigma-Delta ADC, flow rate sensing, plus many more. Check the Microchip web page (www.microchip.com) and the latest “Product Selector Guide” (DS00148) for the complete list of demonstration, development and evaluation kits. © 2007 Microchip Technology Inc. ® ...

Page 135

... Exposure to maximum rating conditions for extended periods may affect device reliability. Note: Voltage spikes below V SS Thus, a series resistor of 50-100 pulling this pin directly to V © 2007 Microchip Technology Inc. PIC16F627A/628A/648A ............................................................................................-0.3 to +14V SS ....................................................................................-0. )..................................................................................................................... ± )............................................................................................................... ± ...

Page 136

... The shaded region indicates the permissible combinations of voltage and frequency. PIC16LF627A/628A/648A VOLTAGE-FREQUENCY GRAPH, -40°C ≤ TA ≤ +85°C FIGURE 17-2: 6.0 5.5 5.0 4 (VOLTS) 4.0 3.5 3.0 2.5 2.0 0 Note: The shaded region indicates the permissible combinations of voltage and frequency. DS40044F-page 134 4 10 FREQUENCY (MHz FREQUENCY (MHz © 2007 Microchip Technology Inc. ...

Page 137

... Data in “Typ” column is at 5.0V, 25°C, unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: This is the limit to which V DD © 2007 Microchip Technology Inc. PIC16F627A/628A/648A Standard Operating Conditions (unless otherwise stated) -40°C ≤ Ta ≤ +85°C for industrial Operating temperature Standard Operating Conditions (unless otherwise stated) -40° ...

Page 138

... WDT Current BOR Current Comparator Current (Both comparators enabled) V Current REF T1O Current kHz OSC LP Oscillator Mode MHz OSC XT Oscillator Mode MHz OSC XT Oscillator Mode MHz OSC INTOSC MHz OSC HS Oscillator Mode © 2007 Microchip Technology Inc. ...

Page 139

... The “Δ” current is the additional current consumed when this peripheral is enabled. This current should be added to the base consumption. © 2007 Microchip Technology Inc. PIC16F627A/628A/648A Standard Operating Conditions (unless otherwise stated) -40°C ≤ Ta ≤ +125°C for extended Operating temperature Min† ...

Page 140

... 7.0 mA 4.5 V, +85° +125° -3.0 mA 4.5 V, -40° to +85° -2.5 mA 4.5 V, +85° +125°C V RA4 pin PIC16F627A/628A/648A, PIC16LF627A/628A/648A pF In XT, HS and LP modes when external clock used to drive OSC1. pF © 2007 Microchip Technology Inc. ...

Page 141

... Note 1: Refer to Section 13.7 “Using the Data EEPROM” for a more detailed discussion on data EEPROM endurance. © 2007 Microchip Technology Inc. PIC16F627A/628A/648A PIC16LF627A/628A/648A (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial and -40° ...

Page 142

... V = 3.0V to 5.5V DD -85° to +125° 2.0V to 3.0V DD -40° to +85°C μ s Units Comments LSb Low Range (VRR = 1) LSb High Range (VRR = 0) LSb Low Range (VRR = 1) LSb High Range (VRR = 0) Ω μ s output signal on RA2 REF © 2007 Microchip Technology Inc. ...

Page 143

... Fall H High I Invalid (High-impedance) L Low FIGURE 17-3: LOAD CONDITIONS Load Condition 1 Pin R = 464Ω for all pins except OSC2 for OSC2 output © 2007 Microchip Technology Inc. PIC16F627A/628A/648A T osc Load Condition Pin V SS Time ...

Page 144

... XT and RC Osc mode ns HS, EC Osc mode μs LP Osc mode ns RC Osc mode ns XT Osc mode ns HS Osc mode μs LP Osc mode ns INTOSC mode (fast) μs INTOSC mode (slow 4/F CY OSC ns XT oscillator, T L/H duty OSC cycle — 5.0V DD © 2007 Microchip Technology Inc. ...

Page 145

... Oscillator Wake-up from Sleep IOSCST start-up time Legend: TBD = To Be Determined. * Characterized but not tested. FIGURE 17-5: CLKOUT AND I/O TIMING Q4 OSC1 CLKOUT I/O Pin (input) I/O Pin Old Value (output) © 2007 Microchip Technology Inc. PIC16F627A/628A/648A Min Typ Max Units — 4 — MHz 3.96 4 4.04 MHz V MHz 2.0V ≤ ...

Page 146

... PIC16F62XA — PIC16LF62XA — — PIC16F62XA T +200 ns* OSC PIC16LF62XA T +400 ns* OSC 0 PIC16F62XA — PIC16LF62XA — 100* 200 © 2007 Microchip Technology Inc. Max Units 75 200* ns — 400 200* ns — 400 100* ns — 200 100* ns — ...

Page 147

... Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. FIGURE 17-8: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS RA4/T0CKI/CMP2 RB6/T1OSO/T1CKI/PGC TMR0 OR TMR1 © 2007 Microchip Technology Inc. PIC16F627A/628A/648A V BOR 35 Min Typ† Max ...

Page 148

... OSC — ns — ns — ns — ns — prescale value (2, 4, ..., 256) — ns — ns — ns — ns — ns — ns — ns — ns — ns — ns — prescale value ( — — — ns — ns (1) — kHz 7T — OSC © 2007 Microchip Technology Inc. ...

Page 149

... F CCP output fall time CC * These parameters are characterized but not tested. † Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. © 2007 Microchip Technology Inc. PIC16F627A/628A/648A ...

Page 150

... PIC16F627A/628A/648A NOTES: DS40044F-page 148 © 2007 Microchip Technology Inc. ...

Page 151

... FIGURE 18-1: TYPICAL BASELINE I 160 140 120 100 2.0 2.5 © 2007 Microchip Technology Inc. PIC16F627A/628A/648A ° ° vs -40°C 0°C +25°C 3.0 3.5 4 ...

Page 152

... PIC16F627A/628A/648A FIGURE 18-2: TYPICAL BASELINE I 300 280 260 240 220 200 180 160 140 120 100 2.0 2.5 FIGURE 18-3: TYPICAL BASELINE CURRENT I 2.4 2.2 2.0 1.8 1.6 1.4 1.2 1.0 2.0 2.5 3.0 DS40044F-page 150 ° vs +85°C 3.0 3.5 4.0 V (Volts) DD vs. V (125 PD DD +125°C 3.5 4.0 4.5 V (Volts) DD 4.5 5.0 5.5 ° C) 5.0 5.5 © 2007 Microchip Technology Inc. ...

Page 153

... FIGURE 18-4: TYPICAL BOR 4.5 4.6 4.7 FIGURE 18-5: TYPICAL SINGLE COMPARATOR 2.5 © 2007 Microchip Technology Inc. PIC16F627A/628A/648A vs 4.8 4.9 5.0 5.1 5.2 V (Volts 3.5 4 4.5 V (Volts) DD 125°C 85°C 25°C 0°C -40°C 5.3 5.4 5.5 125°C 85°C 25°C 0° ...

Page 154

... REF 100 2.0 2.5 3.0 FIGURE 18-7: TYPICAL WDT 2.0 2.5 3.0 DS40044F-page 152 I vs 3.5 4.0 4.5 V (Volts 3.5 4.0 4.5 V (Volts) DD 125°C 85°C 25°C 0°C -40°C 5.0 5.5 125°C 85°C 25°C 0°C -40°C 5.0 5.5 © 2007 Microchip Technology Inc. ...

Page 155

... FIGURE 18-8: AVERAGE 2.5 FIGURE 18-9: TYPICAL INTERNAL OSCILLATOR FREQUENCY vs. TEMPERATURE VOLTS DD 5.0% 4.0% 3.0% 2.0% 1.0% 0.0% -1.0% -2.0% -3.0% -4.0% -5.0% -40 © 2007 Microchip Technology Inc. PIC16F627A/628A/648A _TIMER1 3 3.5 4 4 Temperature (ºC) -40C 0C 25C 85C 125 5 5.5 125 DS40044F-page 153 ...

Page 156

... PIC16F627A/628A/648A FIGURE 18-10: TYPICAL INTERNAL OSCILLATOR FREQUENCY vs. TEMPERATURE VOLTS DD 5.0% 4.0% 3.0% 2.0% 1.0% 0.0% -1.0% -2.0% -3.0% -4.0% -5.0% -40 FIGURE 18-11: TYPICAL INTERNAL OSCILLATOR FREQUENCY vs. TEMPERATURE VOLTS DD 5.0% 4.0% 3.0% 2.0% 1.0% 0.0% -1.0% -2.0% -3.0% -4.0% -5.0% -40 DS40044F-page 154 25 85 Temperature (º Temperature (ºC) 125 125 © 2007 Microchip Technology Inc. ...

Page 157

... FIGURE 18-12: TYPICAL INTERNAL OSCILLATOR DEVIATION vs. V 5.0% 4.0% 3.0% 2.0% 1.0% 0.0% -1.0% -2.0% -3.0% -4.0% -5.0% 2 2.5 FIGURE 18-13: TYPICAL INTERNAL OSCILLATOR FREQUENCY vs. V -40°C TO 85°C 5.0% 4.0% 3.0% 2.0% 1.0% 0.0% -1.0% -2.0% -3.0% -4.0% -5.0% 2 2.5 © 2007 Microchip Technology Inc. PIC16F627A/628A/648A 3 3.5 4 4 3.5 4 4 25°C – 4 MHz MODE DD 5 5.5 TEMPERATURE = DD 5 5.5 DS40044F-page 155 ...

Page 158

... FIGURE 18-14: INTERNAL OSCILLATOR I 1.40 1.20 1.00 0.80 0.60 0.40 0.20 0.00 2 2.5 FIGURE 18-15: TYPICAL INTERNAL OSCILLATOR FREQUENCY vs. V MODE 2.5 DS40044F-page 156 vs. V – 4 MHz MODE Avg - 3.5 4 4 3.5 4 4 5.5 AT 25°C – SLOW DD 5 5.5 © 2007 Microchip Technology Inc. ...

Page 159

... FIGURE 18-17: SUPPLY CURRENT (I 500 450 400 350 300 250 200 150 100 2.0 2.5 3.0 © 2007 Microchip Technology Inc. PIC16F627A/628A/648A vs. V – SLOW MODE Avg - 3.5 4 4.5 V ( MHz (XT OSCILLATOR MODE OSC 3.5 4 ...

Page 160

... FIGURE 18-19: SUPPLY CURRENT (I 4.0 3.5 3.0 2.5 2.0 4.5 4.6 4.7 4.8 DS40044F-page 158 vs MHz (XT OSCILLATOR MODE OSC 3.0 3.5 4.0 4.5 V (Volts vs MHz (HS OSCILLATOR MODE OSC 4.9 5.0 5.1 5.2 V (Volts) DD 125°C 85°C 25°C 0°C -40°C 5.0 5.5 125°C 85°C 25°C 0°C -40°C 5.3 5.4 5.5 © 2007 Microchip Technology Inc. ...

Page 161

... FIGURE 18-20: TYPICAL WDT PERIOD vs 2.5 © 2007 Microchip Technology Inc. PIC16F627A/628A/648A (-40°C TO +125°C) DD WDT Time-out 3 3.5 4 4.5 V ( 125 5 5.5 DS40044F-page 159 ...

Page 162

... PIC16F627A/628A/648A NOTES: DS40044F-page 160 © 2007 Microchip Technology Inc. ...

Page 163

... In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. © 2007 Microchip Technology Inc. PIC16F627A/628A/648A Example PIC16F627A e -I/P 0410017 Example PIC16F628A e -E/SO 0410017 Example PIC16F648A -I/SS e 0410017 Example 16F628A ...

Page 164

... D .880 L .115 c .008 b1 .045 b .014 eB – NOM MAX 18 – .210 .130 .195 – – .310 .325 .250 .280 .900 .920 .130 .150 .010 .014 .060 .070 .018 .022 – .430 Microchip Technology Drawing C04-007B © 2007 Microchip Technology Inc. ...

Page 165

... Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side. 4. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. © 2007 Microchip Technology Inc. PIC16F627A/628A/648A E E1 α ...

Page 166

... REF: Reference Dimension, usually without tolerance, for information purposes only. DS40044F-page 164 Units MILLIMETERS Dimension Limits MIN NOM 0.65 BSC A – – A2 1.65 1.75 A1 0.05 – E 7.40 7.80 E1 5.00 5.30 D 6.90 7.20 L 0.55 0.75 L1 1.25 REF c 0.09 – φ 0° 4° b 0.22 – Microchip Technology Drawing C04-072B φ L MAX 2.00 1.85 – 8.20 5.60 7.50 0.95 0.25 8° 0.38 © 2007 Microchip Technology Inc. ...

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... Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Package is saw singulated. 3. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. © 2007 Microchip Technology Inc. PIC16F627A/628A/648A EXPOSED PAD E ...

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... PIC16F627A/628A/648A NOTES: DS40044F-page 166 © 2007 Microchip Technology Inc. ...

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... Microchip Technology Inc. PIC16F627A/628A/648A APPENDIX B: The differences between the PIC16F627A/628A/648A devices listed in this data sheet are shown in Table B-1. TABLE B-1: DEVICE DIFFERENCES Device Program PIC16F627A 1024 x 14 PIC16F628A 2048 x 14 PIC16F648A 4096 x 14 Replaced DEVICE DIFFERENCES Memory Flash RAM EEPROM ...

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... These differences may cause this device to perform differently in your application than the earlier version of this device. MIGRATING FROM ® OTHER PIC DEVICES web site for availability web site for availability © 2007 Microchip Technology Inc. ...

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... To register, access the Microchip web site at www.microchip.com, click on Customer Change Notification and follow the registration instructions. © 2007 Microchip Technology Inc. PIC16F627A/628A/648A CUSTOMER SUPPORT Users of Microchip products can receive assistance through several channels: • ...

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... What deletions from the document could be made without affecting the overall usefulness there any incorrect or misleading information (what and where)? 7. How would you improve this document? DS40044F-page 170 Total Pages Sent ________ FAX: (______) _________ - _________ N Literature Number: DS40044F © 2007 Microchip Technology Inc. ...

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... CCPR1L Register ............................................... 55 CCP2 .......................................................................... 55 Compare Mode. See Compare PWM Mode. See PWM Timer Resources......................................................... 55 CCP1CON Register ............................................................ 55 CCP1M Bits ................................................................ 55 CCP1X:CCP1Y Bits .................................................... 55 © 2007 Microchip Technology Inc. PIC16F627A/628A/648A CCP2CON Register CCP2M<3:2> Bits....................................................... 55 CCP2X:CCP2Y Bits.................................................... 55 Clocking Scheme/Instruction Cycle .................................... 13 CLRF Instruction............................................................... 119 CLRW Instruction.............................................................. 120 CLRWDT Instruction......................................................... 120 CMCON Register ...

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... PORTB ............................................................................... 36 PORTB Interrupt ............................................................... 108 Power Control/Status Register (PCON)............................ 102 Power-Down Mode (Sleep)............................................... 110 Power-On Reset (POR) .................................................... 101 Power-up Timer (PWRT) .................................................. 101 PR2 Register ................................................................ 52, 58 Program Memory Organization........................................... 15 PWM (CCP Module) ........................................................... 58 Block Diagram ............................................................ 58 Simplified PWM .................................................. 58 CCPR1H:CCPR1L Registers...................................... 58 © 2007 Microchip Technology Inc. ...

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... CCP1CON (CCP Operation)....................................... 55 CMCON (Comparator Configuration).......................... 61 CONFIG (Configuration Word).................................... 96 EECON1 (EEPROM Control Register 1) .................... 90 INTCON (Interrupt Control)......................................... 24 Maps PIC16F627A ................................................. 16, 17 PIC16F628A ................................................. 16, 17 OPTION_REG (Option) .............................................. 23 PCON (Power Control) ............................................... 27 PIE1 (Peripheral Interrupt Enable 1)........................... 25 PIR1 (Peripheral Interrupt Register 1) ........................ 26 Status.......................................................................... 22 T1CON Timer1 Control).............................................. 48 T2CON Timer2 Control) ...

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... Synchronous Slave Mode ........................................... 87 Synchronous Slave Reception .................................... 88 Synchronous Slave Transmit ...................................... 87 V Voltage Reference Configuration............................................................... 67 Voltage Reference Module ......................................... 67 W Watchdog Timer (WDT) .................................................... 109 WWW Address.................................................................. 169 WWW, On-Line Support........................................................ 3 X XORLW Instruction ........................................................... 128 XORWF Instruction ........................................................... 128 DS40044F-page 174 © 2007 Microchip Technology Inc. ...

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... Range -40°C to+125°C Package PDIP SO = SOIC (Gull Wing, 7.50 mm body SSOP (5. QFN (28 Lead) © 2007 Microchip Technology Inc. PIC16F627A/628A/648A XXX Examples: Pattern a) PIC16F627A - E/P 301 = Extended Temp., PDIP package, 20 MHz, normal V its, QTP pattern #301. range 3. PIC16LF627A - I/SO = Industrial Temp ...

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... Taiwan - Kaohsiung Tel: 886-7-536-4818 Fax: 886-7-536-4803 Taiwan - Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 Thailand - Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350 © 2007 Microchip Technology Inc. EUROPE Austria - Wels Tel: 43-7242-2244-39 Fax: 43-7242-2244-393 Denmark - Copenhagen Tel: 45-4450-2828 Fax: 45-4485-2829 France - Paris ...

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