PIC16F877 Microchip Technology Inc., PIC16F877 Datasheet

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PIC16F877

Manufacturer Part Number
PIC16F877
Description
Manufacturer
Microchip Technology Inc.
Datasheet

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PIC16F87X
Data Sheet
28/40-Pin 8-Bit CMOS FLASH
Microcontrollers
2001 Microchip Technology Inc.
DS30292C

Related parts for PIC16F877

PIC16F877 Summary of contents

Page 1

... Microchip Technology Inc. 28/40-Pin 8-Bit CMOS FLASH PIC16F87X Data Sheet Microcontrollers DS30292C ...

Page 2

... Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights. The Microchip logo and name are registered trademarks of Microchip Technology Inc. in the U.S.A. and other countries. All rights reserved. All other trademarks mentioned herein are the property of their respective companies. No licenses are conveyed, implicitly or otherwise, under any intellectual prop- erty rights.” ...

Page 3

... CMOS FLASH Microcontrollers Devices Included in this Data Sheet: • PIC16F873 • PIC16F876 • PIC16F874 • PIC16F877 Microcontroller Core Features: • High performance RISC CPU • Only 35 single word instructions to learn • All single cycle instructions except for program branches which are two cycle • ...

Page 4

... RB4 RB3/PGM 24 23 RB2 22 RB1 21 RB0/INT RC7/RX/DT 17 RC6/TX/CK RC5/SDO 16 RC4/SDI/SDA 15 PLCC RA4/T0CKI 7 RA5/AN4/SS 8 RE0/RD/AN5 9 RE1/WR/AN6 10 RE2/CS/AN7 PIC16F877 PIC16F874 OSC1/CLKIN 14 OSC2/CLKOUT 15 RC0/T1OSO/T1CK1 RC0/T1OSO/T1CKI OSC2/CLKOUT 31 OSC1/CLKIN RE2/AN7/CS 27 RE1/AN6/WR ...

Page 5

... Ports A,B,C Ports A,B,C,D MSSP, USART MSSP, USART — PSP 5 input channels 8 input channels 5 input channels 35 instructions 35 instructions PIC16F87X PIC16F876 PIC16F877 MHz MHz POR, BOR POR, BOR (PWRT, OST) (PWRT, OST 368 368 256 256 13 14 Ports A,B,C Ports A,B,C,D,E ...

Page 6

... When contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (include liter- ature number) you are using. Customer Notification System Register on our web site at www.microchip.com/cn to receive the most current information on all of our products. DS30292C-page 4 2001 Microchip Technology Inc. ...

Page 7

... There are four devices (PIC16F873, PIC16F874, PIC16F876 and PIC16F877) covered by this data sheet. The PIC16F876/873 devices come in 28-pin packages and the PIC16F877/874 devices come in 40-pin packages. The Parallel Slave Port is not implemented on the 28-pin devices. The following device block diagrams are sorted by pin number ...

Page 8

... PIC16F87X FIGURE 1-2: PIC16F874 AND PIC16F877 BLOCK DIAGRAM Program Device Data Memory FLASH PIC16F874 4K 192 Bytes PIC16F877 8K 368 Bytes 13 FLASH Program Memory Program 14 Bus Instruction reg 8 Instruction Decode & Control Timing Generation OSC1/CLKIN OSC2/CLKOUT MCLR Timer0 Timer1 Data EEPROM CCP1,2 Note 1: Higher order bits are from the STATUS register. ...

Page 9

... Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt. 2: This buffer is a Schmitt Trigger input when used in Serial Programming mode. 3: This buffer is a Schmitt Trigger input when configured in RC oscillator mode and a CMOS input otherwise. 2001 Microchip Technology Inc. I/O/P Buffer ...

Page 10

... PIC16F87X TABLE 1-2: PIC16F874 AND PIC16F877 PINOUT DESCRIPTION DIP PLCC QFP Pin Name Pin# Pin# Pin# OSC1/CLKIN 13 14 OSC2/CLKOUT 14 15 MCLR RA0/AN0 2 3 RA1/AN1 3 4 RA2/AN2 REF RA3/AN3 REF RA4/T0CKI 6 7 RA5/SS/AN4 7 8 RB0/INT 33 36 RB1 34 37 RB2 ...

Page 11

... TABLE 1-2: PIC16F874 AND PIC16F877 PINOUT DESCRIPTION (CONTINUED) DIP PLCC QFP Pin Name Pin# Pin# Pin# RC0/T1OSO/T1CKI 15 16 RC1/T1OSI/CCP2 16 18 RC2/CCP1 17 19 RC3/SCK/SCL 18 20 RC4/SDI/SDA 23 25 RC5/SDO 24 26 RC6/TX/ RC7/RX/ RD0/PSP0 19 21 RD1/PSP1 20 22 RD2/PSP2 21 23 RD3/PSP3 22 24 RD4/PSP4 27 30 ...

Page 12

... PIC16F87X NOTES: DS30292C-page 10 2001 Microchip Technology Inc. ...

Page 13

... Page 3 2001 Microchip Technology Inc. 2.1 Program Memory Organization The PIC16F87X devices have a 13-bit program counter capable of addressing program memory space. The PIC16F877/876 devices have words of FLASH PIC16F873/874 devices have 4K x 14. Accessing a location above the physically implemented address will cause a wraparound ...

Page 14

... Note: EEPROM Data Memory description can be found in Section 4.0 of this data sheet 2.2.1 GENERAL PURPOSE REGISTER 2 FILE 3 The register file can be accessed either directly, or indi- rectly through the File Select Register (FSR). 2001 Microchip Technology Inc. ...

Page 15

... FIGURE 2-3: PIC16F877/876 REGISTER FILE MAP File File Address Address (*) Indirect addr. Indirect addr. 00h 01h TMR0 OPTION_REG 02h PCL STATUS 03h 04h FSR 05h PORTA PORTB 06h PORTC 07h (1) 08h PORTD (1) 09h PORTE PCLATH 0Ah 0Bh INTCON 0Ch PIR1 0Dh PIR2 ...

Page 16

... PCLATH 18Ah 10Bh INTCON 18Bh 10Ch EECON1 18Ch EECON2 10Dh 18Dh 10Eh (2) Reserved 18Eh 10Fh Reserved (2) 18Fh 110h 190h 1A0h 120h accesses A0h - FFh 1EFh 16Fh 1F0h 170h 17Fh 1FFh Bank 3 2001 Microchip Technology Inc. ...

Page 17

... PORTD, PORTE, TRISD, and TRISE are not physically implemented on PIC16F873/876 devices; read as ‘0’. 5: PIR2<6> and PIE2<6> are reserved on these devices; always maintain these bits clear. 2001 Microchip Technology Inc. The Special Function Registers can be classified into two sets: core (CPU) and peripheral. Those registers associated with the core functions are described in detail in this section ...

Page 18

... 0000 0000 — — — — — — TRMT TX9D 95 0000 -010 97 0000 0000 — — — — — — — — 116 xxxx xxxx PCFG1 PCFG0 112 0--- 0000 2001 Microchip Technology Inc. ...

Page 19

... Bits PSPIE and PSPIF are reserved on PIC16F873/876 devices; always maintain these bits clear. 3: These registers can be addressed from any bank. 4: PORTD, PORTE, TRISD, and TRISE are not physically implemented on PIC16F873/876 devices; read as ‘0’. 5: PIR2<6> and PIE2<6> are reserved on these devices; always maintain these bits clear. 2001 Microchip Technology Inc. Bit 5 Bit 4 Bit 3 ...

Page 20

... See the SUBLW and SUBWF instructions for examples. R/W-0 R-1 R-1 RP1 RP0 Writable bit U = Unimplemented bit, read as ‘0’ ’1’ = Bit is set ’0’ = Bit is cleared R/W-x R/W-x R/W bit Bit is unknown 2001 Microchip Technology Inc. ...

Page 21

... When using low voltage ICSP programming (LVP) and the pull-ups on PORTB are enabled, bit 3 in the TRISB register must be cleared to disable the pull-up on RB3 and ensure the proper oper- ation of the device 2001 Microchip Technology Inc. Note: To achieve a 1:1 prescaler assignment for the TMR0 register, assign the prescaler to the Watchdog Timer ...

Page 22

... R/W-0 R/W-0 R/W-0 T0IE INTE RBIE W = Writable bit U = Unimplemented bit, read as ‘0’ ’1’ = Bit is set ’0’ = Bit is cleared R/W-0 R/W-0 R/W-x T0IF INTF RBIF bit Bit is unknown 2001 Microchip Technology Inc. ...

Page 23

... TMR1IE: TMR1 Overflow Interrupt Enable bit 1 = Enables the TMR1 overflow interrupt 0 = Disables the TMR1 overflow interrupt Note 1: PSPIE is reserved on PIC16F873/876 devices; always maintain this bit clear. Legend Readable bit - n = Value at POR 2001 Microchip Technology Inc. Note: Bit PEIE (INTCON<6>) must be set to enable any peripheral interrupt. R/W-0 R/W-0 R/W-0 ...

Page 24

... R-0 R-0 R/W-0 R/W-0 RCIF TXIF SSPIF CCP1IF W = Writable bit U = Unimplemented bit, read as ‘0’ ’1’ = Bit is set ’0’ = Bit is cleared R/W-0 R/W-0 TMR2IF TMR1IF bit Bit is unknown 2001 Microchip Technology Inc. ...

Page 25

... Unimplemented: Read as '0' bit 0 CCP2IE: CCP2 Interrupt Enable bit 1 = Enables the CCP2 interrupt 0 = Disables the CCP2 interrupt Legend Readable bit - n = Value at POR 2001 Microchip Technology Inc. U-0 R/W-0 R/W-0 — EEIE BCLIE W = Writable bit U = Unimplemented bit, read as ‘0’ ’1’ = Bit is set ’ ...

Page 26

... U-0 R/W-0 R/W-0 U-0 — EEIF BCLIF W = Writable bit U = Unimplemented bit, read as ‘0’ ’1’ = Bit is set ’0’ = Bit is cleared U-0 R/W-0 — — CCP2IF bit Bit is unknown 2001 Microchip Technology Inc. ...

Page 27

... No Brown-out Reset occurred Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs) Legend Readable bit - n = Value at POR  2001 Microchip Technology Inc. Note: BOR is unknown on POR. It must be set by the user and checked on subsequent RESETS to see if BOR is clear, indicating a brown-out has occurred. The BOR status bit is a “ ...

Page 28

... BCF PCLATH,4 BSF PCLATH,3 CALL SUB1_P1 : : ORG 0x900 SUB1_P1 : : RETURN Therefore, manipulation of the CALL OF A SUBROUTINE IN PAGE 1 FROM PAGE 0 ;Select page 1 ;(800h-FFFh) ;Call subroutine in ;page 1 (800h-FFFh) ;page 1 (800h-FFFh) ;called subroutine ;page 1 (800h-FFFh) ;return to ;Call subroutine ;in page 0 ;(000h-7FFh) 2001 Microchip Technology Inc. ...

Page 29

... Bank Select Location Select 00h Data (1) Memory 7Fh Bank 0 Note 1: For register file map detail, see Figure 2-3. 2001 Microchip Technology Inc. A simple program to clear RAM locations 20h-2Fh using indirect addressing is shown in Example 2-2. EXAMPLE 2-2: MOVLW 0x20 MOVWF FSR NEXT CLRF INCF BTFSS FSR,4 ...

Page 30

... PIC16F87X NOTES: DS30292C-page 28 2001 Microchip Technology Inc. ...

Page 31

... MOVWF ADCON1 ; as digital inputs MOVLW 0xCF ; Value used to ; initialize data ; direction MOVWF TRISA ; Set RA<3:0> as inputs ; RA<5:4> as outputs ; TRISA<7:6>are always ; read as ’0’. 2001 Microchip Technology Inc. PIC16F87X FIGURE 3-1: BLOCK DIAGRAM OF RA3:RA0 AND RA5 PINS Data Latch Data Bus Port CK Q TRIS Latch ...

Page 32

... Input/output or slave select input for synchronous serial port or analog input. Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 RA5 RA4 RA3 RA2 RA1 PORTA Data Direction Register — — PCFG3 PCFG2 PCFG1 PCFG0 Value on: Value on all Bit 0 POR, other BOR RESETS RA0 --0x 0000 --0u 0000 --11 1111 --11 1111 --0- 0000 --0- 0000 2001 Microchip Technology Inc. ...

Page 33

... PORTB. The “mismatch” outputs of RB7:RB4 are OR’ed together to generate the RB Port Change Interrupt with flag bit RBIF (INTCON<0>). 2001 Microchip Technology Inc. This interrupt can wake the device from SLEEP. The user, in the Interrupt Service Routine, can clear the ...

Page 34

... Bit 3 Bit 2 Bit 1 Bit 0 RB6 RB5 RB4 RB3 RB2 INTEDG T0CS T0SE PSA PS2 Value on: Value on POR, all other BOR RESETS RB1 RB0 xxxx xxxx uuuu uuuu 1111 1111 1111 1111 PS1 PS0 1111 1111 1111 1111 2001 Microchip Technology Inc. ...

Page 35

... Peripheral Input Note 1: I/O pins have diode protection Port/Peripheral select signal selects between port data and peripheral output. 3: Peripheral OE (output enable) is only activated if peripheral select is active. 2001 Microchip Technology Inc. FIGURE 3-6: Port/Peripheral Select Peripheral Data Out Data Bus D WR Port ...

Page 36

... Input/output port pin or USART Asynchronous Receive or Synchronous Data. Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 RC5 RC4 RC3 RC2 RC1 2 C mode). Value on: Value on all Bit 0 POR, other BOR RESETS RC0 xxxx xxxx uuuu uuuu 1111 1111 1111 1111 2001 Microchip Technology Inc. ...

Page 37

... RD7 RD6 RD5 88h TRISD PORTD Data Direction Register 89h TRISE IBF OBF IBOV PSPMODE Legend unknown unchanged unimplemented, read as '0'. Shaded cells are not used by PORTD. 2001 Microchip Technology Inc. FIGURE 3-7: Data Bus WR Port WR TRIS RD TRIS RD Port Note 1: I/O pins have protection diodes to V (1) Input/output port pin or parallel slave port bit0 ...

Page 38

... I/O PORT MODE) (1) I/O pin Data Latch TRIS Latch D Q Schmitt CK Trigger Input Buffer and Value on Value on: Bit 0 all other POR, BOR RESETS RE1 RE0 ---- -xxx ---- -uuu 0000 -111 0000 -111 PCFG0 --0- 0000 --0- 0000 2001 Microchip Technology Inc. ...

Page 39

... Bit1: Direction Control bit for pin RE1/WR/AN6 1 = Input 0 = Output bit 0 Bit0: Direction Control bit for pin RE0/RD/AN5 1 = Input 0 = Output Legend Readable bit - n = Value at POR 2001 Microchip Technology Inc. R-0 R/W-0 R/W-0 U-0 OBF IBOV PSPMODE W = Writable bit U = Unimplemented bit, read as ‘0’ ’1’ = Bit is set ’ ...

Page 40

... Port One bit of PORTD Set Interrupt Flag PSPIF(PIR1<7>) Note 1: I/O pins have protection diodes to V PORTD AND PORTE BLOCK DIAGRAM (PARALLEL SLAVE PORT RDx pin CK TTL Read TTL RD Chip Select TTL CS Write WR TTL and 2001 Microchip Technology Inc. ...

Page 41

... ADIE 9Fh ADCON1 ADFM — Legend unknown unchanged unimplemented, read as '0'. Shaded cells are not used by the Parallel Slave Port. Note 1: Bits PSPIE and PSPIF are reserved on the PIC16F873/876; always maintain these bits clear. 2001 Microchip Technology Inc ...

Page 42

... PIC16F87X NOTES: DS30292C-page 40 2001 Microchip Technology Inc. ...

Page 43

... PIC16F873/874, or 0000h to 3FFFh for the PIC16F876/877. Addresses outside of this range do not wrap around to 0000h (i.e., 4000h does not map to 0000h on the PIC16F877). 4.1 EECON1 and EECON2 Registers The EECON1 register is the control register for config- uring and initiating the access ...

Page 44

... MCLR Reset, or WDT Time- out Reset, during normal operation. U-0 U-0 U-0 R/W-x — — — WRERR W = Writable bit U = Unimplemented bit, read as ‘0’ ’1’ = Bit is set ’0’ = Bit is cleared R/W-0 R/S-0 R/S-0 WREN WR RD bit Bit is unknown 2001 Microchip Technology Inc. ...

Page 45

... This is a sequence of five instructions that must be executed without interrup- tions. The firmware should verify that a write is not in progress, before starting another cycle. 2001 Microchip Technology Inc. PIC16F87X The steps to write to EEPROM data memory are step 10 is not implemented, check the WR bit to see if a write is in progress ...

Page 46

... Write AAh to EECON2 in two steps (first to W, then to EECON2) • Set the WR bit 7. Execute two NOP instructions to allow the micro- controller to setup for write operation. 8. Enable interrupts (if using interrupts). 9. Clear the WREN bit to disable program operations. 2001 Microchip Technology Inc. ...

Page 47

... This should be used in applications where excessive writes can stress bits near the speci- fied endurance limits. 2001 Microchip Technology Inc. PIC16F87X 4.7 Protection Against Spurious Writes ...

Page 48

... Bit 1 Bit 0 POR, all other BOR RESETS RBIF 0000 000x 0000 000u xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu WR RD x--- x000 x--- u000 — — — CCP2IE -r-0 0--0 -r-0 0--0 — CCP2IF -r-0 0--0 -r-0 0--0 2001 Microchip Technology Inc. ...

Page 49

... Watchdog Timer PSA WDT Enable bit Note: T0CS, T0SE, PSA, PS2:PS0 are (OPTION_REG<5:0>). 2001 Microchip Technology Inc. Counter mode is selected by setting bit T0CS (OPTION_REG<5>). In Counter mode, Timer0 will increment either on every rising, or falling edge of pin RA4/T0CKI. The incrementing edge is determined by the Timer0 (OPTION_REG< ...

Page 50

... R/W-1 R/W-1 R/W-1 T0CS T0SE PSA 128 W = Writable bit U = Unimplemented bit, read as ‘0’ ’1’ = Bit is set ’0’ = Bit is cleared R/W-1 R/W-1 R/W-1 PS2 PS1 PS0 bit Bit is unknown 2001 Microchip Technology Inc. ...

Page 51

... Timer0 Module’s Register 0Bh,8Bh, INTCON GIE 10Bh,18Bh 81h,181h OPTION_REG RBPU INTEDG T0CS T0SE Legend unknown unchanged unimplemented locations read as '0'. Shaded cells are not used by Timer0. 2001 Microchip Technology Inc. Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 PEIE T0IE INTE RBIE T0IF PSA ...

Page 52

... PIC16F87X NOTES: DS30292C-page 50 2001 Microchip Technology Inc. ...

Page 53

... TMR1ON: Timer1 On bit 1 = Enables Timer1 0 = Stops Timer1 Legend Readable bit - n = Value at POR 2001 Microchip Technology Inc. In Timer mode, Timer1 increments every instruction cycle. In Counter mode, it increments on every rising edge of the external clock input. Timer1 can be enabled/disabled by setting/clearing control bit TMR1ON (T1CON<0>). ...

Page 54

... The prescaler, however, will continue to increment. TMR1 TMR1L TMR1ON T1SYNC On/Off 1 Prescaler T1OSCEN F /4 OSC Enable Internal 0 (1) Oscillator Clock T1CKPS1:T1CKPS0 TMR1CS Synchronized 0 Clock Input 1 Synchronize det 2 Q Clock 2001 Microchip Technology Inc. ...

Page 55

... Table 6-1 shows the capacitor selection for the Timer1 oscillator. The Timer1 oscillator is identical to the LP oscillator. The user must provide a software time delay to ensure proper oscillator start-up. 2001 Microchip Technology Inc. PIC16F87X TABLE 6-1: CAPACITOR SELECTION FOR THE TIMER1 OSCILLATOR Osc Type Freq ...

Page 56

... Bit 1 Bit 0 POR, all other BOR RESETS 0000 000x 0000 000u INTF RBIF TMR2IF TMR1IF 0000 0000 0000 0000 TMR2IE TMR1IE 0000 0000 0000 0000 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu TMR1CS TMR1ON --00 0000 --uu uuuu 2001 Microchip Technology Inc. ...

Page 57

... T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits 00 = Prescaler Prescaler Prescaler is 16 Legend Readable bit - n = Value at POR 2001 Microchip Technology Inc. Register 7-1 shows the Timer2 control register. Additional information on timer modules is available in the PICmicro™ Mid-Range MCU Family Reference Manual (DS33023). FIGURE 7-1: Sets Flag ...

Page 58

... TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000 Value on: Value on Bit 1 Bit 0 POR, all other BOR RESETS INTF RBIF 0000 000x 0000 000u TMR2IF TMR1IF 0000 0000 0000 0000 TMR2IE TMR1IE 0000 0000 0000 0000 0000 0000 0000 0000 1111 1111 1111 1111 2001 Microchip Technology Inc. ...

Page 59

... The PWMs will have the same frequency and update rate (TMR2 interrupt) PWM Capture None PWM Compare None 2001 Microchip Technology Inc. PIC16F87X CCP2 Module: Capture/Compare/PWM Register2 (CCPR2) is com- prised of two 8-bit registers: CCPR2L (low byte) and CCPR2H (high byte). The CCP2CON register controls the operation of CCP2. The special event trigger is ...

Page 60

... TMR1; CCP2 resets TMR1 and starts an A/D conversion (if A/D module is enabled) 11xx = PWM mode Legend Readable bit - n = Value at POR DS30292C-page 58 U-0 R/W-0 R/W-0 R/W-0 — CCPxX CCPxY CCPxM3 W = Writable bit U = Unimplemented bit, read as ‘0’ ’1’ = Bit is set ’0’ = Bit is cleared R/W-0 R/W-0 R/W-0 CCPxM2 CCPxM1 CCPxM0 bit Bit is unknown 2001 Microchip Technology Inc. ...

Page 61

... CCPR1H Capture and Enable edge detect TMR1H CCP1CON<3:0> Qs 2001 Microchip Technology Inc. 8.1.2 TIMER1 MODE SELECTION Timer1 must be running in Timer mode, or Synchro- nized Counter mode, for the CCP module to use the capture feature. In Asynchronous Counter mode, the capture operation may not work. 8.1.3 ...

Page 62

... The special event trigger output of CCP2 resets the TMR1 register pair and starts an A/D conversion (if the A/D module is enabled). Note: The special event trigger from the CCP1and CCP2 modules will not set inter- Comparator rupt flag bit TMR1IF (PIR1<0>). TMR1L 2001 Microchip Technology Inc. ...

Page 63

... PWM OUTPUT Period Duty Cycle TMR2 = PR2 TMR2 = Duty Cycle TMR2 = PR2 2001 Microchip Technology Inc. 8.3.1 PWM PERIOD The PWM period is specified by writing to the PR2 reg- ister. The PWM period can be calculated using the fol- lowing formula: PWM period = [(PR2 • 4 • T PWM frequency is defined [PWM period] ...

Page 64

... TMR2IE TMR1IE 0000 0000 0000 0000 — CCP2IE ---- ---0 ---- ---0 1111 1111 1111 1111 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu 2001 Microchip Technology Inc. ...

Page 65

... CCP2CON — — Legend unknown unchanged unimplemented, read as '0'. Shaded cells are not used by PWM and Timer2. Note 1: Bits PSPIE and PSPIF are reserved on the PIC16F873/876; always maintain these bits clear. 2001 Microchip Technology Inc. Bit 5 Bit 4 Bit 3 Bit 2 T0IE INTE ...

Page 66

... PIC16F87X NOTES: DS30292C-page 64 2001 Microchip Technology Inc. ...

Page 67

... SSP for Slave I C Communication” describes the slave operation of the MSSP module on the PIC16F87X devices. AN735, “Using the PICmicro 2 MSSP Module for Communications” describes the master operation of the MSSP module on the PIC16F87X devices. 2001 Microchip Technology Inc. PIC16F87X ® ® DS30292C-page 65 ...

Page 68

... Value at POR DS30292C-page 66 R-0 R-0 R-0 CKE D specs 2 C mode only mode only mode only modes Writable bit U = Unimplemented bit, read as ‘0’ ’1’ = Bit is set ’0’ = Bit is cleared R-0 R-0 R-0 R bit Bit is unknown 2001 Microchip Technology Inc. ...

Page 69

... C Firmware Controlled Master mode, 7-bit address with START and STOP bit interrupts enabled 2 1111 = I C Firmware Controlled Master mode, 10-bit address with START and STOP bit interrupts enabled 1001, 1010, 1100, 1101 = Reserved Legend Readable bit - n = Value at POR 2001 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 SSPEN CKP SSPM3 SSPM2 ...

Page 70

... C Master mode only Master mode only Master mode only Writable bit U = Unimplemented bit, read as ‘0’ ’1’ = Bit is set ’0’ = Bit is cleared R/W-0 R/W-0 RSEN SEN bit 0 C module is not in the IDLE x = Bit is unknown 2001 Microchip Technology Inc. ...

Page 71

... SS must have TRISA<5> set and register ADCON1 (see Section 11.0: A/D Module) must be set in a way that pin RA5 is configured as a digital I/O 2001 Microchip Technology Inc. PIC16F87X Any serial port function that is not desired may be overridden by programming the corresponding data direction (TRIS) register to the opposite value. ...

Page 72

... When CKE = 1, the SDO data is valid before there is a clock edge on SCK. The change of the input sample is shown based on the state of the SMP bit. The time when the SSPBUF is loaded with the received data is shown. bit6 bit5 bit3 bit4 ) bit2 bit1 bit0 bit0 bit0 2001 Microchip Technology Inc. ...

Page 73

... SCK (CKP = 1) SDO bit7 SDI (SMP = 0) bit7 SSPIF 2001 Microchip Technology Inc. While in SLEEP mode, the slave can transmit/receive data. When a byte is received, the device will wake-up from SLEEP. Note 1: When the SPI module is in Slave mode with SS pin control enabled (SSPCON< ...

Page 74

... SSPM1 D R/W UA Value on: Value on: Bit 0 POR, BOR MCLR, WDT RBIF 0000 000x 0000 000u TMR1IF 0000 0000 0000 0000 TMR1IE 0000 0000 0000 0000 xxxx xxxx uuuu uuuu SSPM0 0000 0000 0000 0000 BF 0000 0000 0000 0000 2001 Microchip Technology Inc. ...

Page 75

... SSP Status Register (SSPSTAT) • Serial Receive/Transmit Buffer (SSPBUF) • SSP Shift Register (SSPSR) - Not directly accessible • SSP Address Register (SSPADD) 2001 Microchip Technology Inc. The SSPCON register allows control of the I tion. Four mode selection bits (SSPCON<3:0>) allow one of the following I 2 • ...

Page 76

... The SSPBUF will be loaded if the SSPOV bit is set and the BF flag is cleared read of the SSPBUF was performed, but the user did not clear the state of the SSPOV bit before the next receive occurred, the ACK is not sent and the SSPBUF is updated. 2001 Microchip Technology Inc. ...

Page 77

... SDA SCL S SSPIF BF (SSPSTAT<0>) SSPOV (SSPCON<6>) 2001 Microchip Technology Inc. Generate ACK SSPBUF Pulse Yes Yes Yes No An SSP interrupt is generated for each data transfer byte. The SSPIF flag bit must be cleared in software and the SSPSTAT register is used to determine the sta- tus of the byte transfer ...

Page 78

... Cleared in software SSPBUF is read R Transmitting Data Not ACK From SSP Interrupt Service Routine Receiving data ACK ’0’ ’1’ 2001 Microchip Technology Inc. ...

Page 79

... Legend unknown unchanged unimplemented, read as '0'. Shaded cells are not used by the SSP in I Note 1: These bits are reserved on PIC16F873/876 devices; always maintain these bits clear. 2: These bits are reserved on these devices; always maintain these bits clear. 2001 Microchip Technology Inc. 9.2.4 EFFECTS OF A RESET A RESET disables the SSP module and terminates the current transfer ...

Page 80

... BCLIF bit. The states where arbitration can be lost are • Address Transfer • Data Transfer • A START Condition • A Repeated START Condition • An Acknowledge Condition SSPM3:SSPM0, SSPADD<6:0> Baud Rate Generator 2001 Microchip Technology Inc. ...

Page 81

... SSPADD register. The baud rate generator will automatically begin counting on a write to the 2001 Microchip Technology Inc. SSPBUF. Once the given operation is complete (i.e., transmission of the last data bit is followed by ACK), the internal clock will automatically stop counting and the SCL pin will remain in its last state ...

Page 82

... Set S bit (SSPSTAT<3>) SDA = 1, At completion of START bit, SCL = 1 Hardware clears SEN bit and sets SSPIF bit T T BRG BRG Write to SSPBUF occurs here 1st Bit T BRG S 03h 02h 2 C module is reset into its IDLE state. 2nd Bit T BRG 2001 Microchip Technology Inc. ...

Page 83

... SCL (no change) SDA Falling edge of ninth clock End of Xmit SCL 2001 Microchip Technology Inc. PIC16F87X Immediately following the SSPIF bit getting set, the user may write the SSPBUF with the 7-bit address in 7-bit mode, or the default first address in 10-bit mode. After the first eight bits are transmitted and an ACK is ...

Page 84

... Acknowledge (ACK = 0), and is set when the slave does not Acknowl- edge (ACK = 1). A slave sends an Acknowledge when it has recognized its address (including a general call), or when the slave has properly received its data. 2001 Microchip Technology Inc. ...

Page 85

... FIGURE 9-14 MASTER MODE TIMING (TRANSMISSION 10-BIT ADDRESS) 2001 Microchip Technology Inc. PIC16F87X DS30292C-page 83 ...

Page 86

... SSPSR, and the BF flag is already set from a previous reception. 9.2.12.3 WCOL Status Flag If the user writes the SSPBUF when a receive is already in progress (i.e., SSPSR is still shifting in a data byte), then WCOL is set and the contents of the buffer are unchanged (the write doesn’t occur). 2001 Microchip Technology Inc. ...

Page 87

... FIGURE 9-15 MASTER MODE TIMING (RECEPTION, 7-BIT ADDRESS) 2001 Microchip Technology Inc. PIC16F87X DS30292C-page 85 ...

Page 88

... WCOL is set and the con- tents of the buffer are unchanged (the write doesn’t occur). ACKEN automatically cleared T T BRG BRG D0 ACK 8 9 Cleared in software Set SSPIF at the end of Acknowledge sequence . The SCL pin is then BRG Cleared in software 2001 Microchip Technology Inc. ...

Page 89

... SDA asserted low before rising edge of clock to setup STOP condition Note one baud rate generator period. BRG 2001 Microchip Technology Inc. while SCL is high, the P bit (SSPSTAT<4>) is set later, the PEN bit is cleared and the SSPIF bit is BRG set (Figure 9-17). ...

Page 90

... A RESET disables the SSP module and terminates the current transfer. SCL = 1, BRG starts counting clock high interval SCL line sampled once every machine cycle (T Hold off BRG until SCL is sampled high BRG BRG 2 C module can receive 4). OSC 2001 Microchip Technology Inc. ...

Page 91

... Data changes while SCL = 0 SDA SCL BCLIF 2001 Microchip Technology Inc START, Repeated START, STOP, or Acknowledge condition was in progress when the bus collision occurred, the condition is aborted, the SDA and SCL lines are de-asserted, and the respective control bits in the SSPCON2 register are cleared. When the user ser- ...

Page 92

... SDA goes low before the SEN bit is set. Set BCLIF, S bit and SSPIF set because SDA = 0, SCL = 1. SEN cleared automatically because of bus collision. SSP module reset into IDLE state. Set BCLIF. SSPIF and BCLIF are cleared in software SSPIF and BCLIF are cleared in software 2001 Microchip Technology Inc. ...

Page 93

... Less than T SDA pulled low by other master. SDA Reset BRG and assert SDA. SCL SEN ’0’ BCLIF S SSPIF 2001 Microchip Technology Inc. SDA = 0, SCL = BRG BRG SCL = 0 before SDA = 0, Bus collision occurs, Set BCLIF SDA = 0, SCL = 1 Set S Set SSPIF ...

Page 94

... Repeated START condition is complete (Figure 9-23). Sample SDA when SCL goes high. If SDA = 0, set BCLIF and release SDA and SCL. Cleared in software T T BRG BRG 2001 Microchip Technology Inc. ’0’ ’0’ Interrupt cleared in software ’0’ ’0’ ...

Page 95

... BCLIF P ’0’ ’0’ SSPIF 2001 Microchip Technology Inc. The STOP condition begins with SDA asserted low. When SDA is sampled low, the SCL pin is allowed to float. When the pin is sampled high (clock arbitration), the baud rate generator is loaded with SSPADD<6:0> ...

Page 96

... DD = 5V±10% and DD min = (5.5-0.4)/0.003 = 1 shown in Figure 9-27. The p for the low level limits DD . Series resistors are optional s due to the specified rise time mode (master or slave). C =10 - 400 pF b 2001 Microchip Technology Inc. ...

Page 97

... TX9D: 9th bit of Transmit Data, can be parity bit Legend Readable bit - n = Value at POR 2001 Microchip Technology Inc. The USART can be configured in the following modes: • Asynchronous (full duplex) • Synchronous - Master (half duplex) • Synchronous - Slave (half duplex) Bit SPEN (RCSTA<7>) and bits TRISC<7:6> have to ...

Page 98

... RX9D: 9th bit of Received Data (can be parity bit, but must be calculated by user firmware) Legend Readable bit - n = Value at POR DS30292C-page 96 R/W-0 R/W-0 R/W-0 RX9 SREN CREN ADDEN W = Writable bit U = Unimplemented bit, read as ‘0’ ’1’ = Bit is set ’0’ = Bit is cleared R-0 R-0 R-x FERR OERR RX9D bit Bit is unknown 2001 Microchip Technology Inc. ...

Page 99

... RX9 99h SPBRG Baud Rate Generator Register Legend unknown unimplemented, read as '0'. Shaded cells are not used by the BRG. 2001 Microchip Technology Inc. It may be advantageous to use the high baud rate (BRGH = 1), even for slower baud clocks. This is because the F OSC baud rate error in some cases. ...

Page 100

... F = 3.6864 MHz OSC SPBRG % value ERROR (decimal 1.2 0 191 32.9 2. 0.9 - 255 230 MHz SPBRG % value (decimal 129 255 - MHz SPBRG % value (decimal 1.71 255 0.16 64 1.72 31 1.36 21 2. 255 - 0 2001 Microchip Technology Inc. ...

Page 101

... TXEN Baud Rate CLK SPBRG Baud Rate Generator 2001 Microchip Technology Inc. enabled/disabled by setting/clearing enable bit TXIE ( PIE1<4>). Flag bit TXIF will be set, regardless of the state of enable bit TXIE and cannot be cleared in soft- ware. It will reset only when new data is loaded into the TXREG register. While flag bit TXIF indicates the status of the TXREG register, another bit TRMT (TXSTA< ...

Page 102

... BOR RESETS R0IF 0000 000x 0000 000u TMR1IF 0000 0000 0000 0000 RX9D 0000 -00x 0000 -00x 0000 0000 0000 0000 TMR1IE 0000 0000 0000 0000 TX9D 0000 -010 0000 -010 0000 0000 0000 0000 2001 Microchip Technology Inc. ...

Page 103

... RC7/RX/DT Pin Buffer and Control SPEN 2001 Microchip Technology Inc. is possible for two bytes of data to be received and transferred to the RCREG FIFO and a third byte to begin shifting to the RSR register. On the detection of the STOP bit of the third byte, if the RCREG register is still full, the overrun error bit OERR (RCSTA< ...

Page 104

... Bit 0 POR, all other BOR RESETS R0IF 0000 000x 0000 000u 0000 0000 0000 0000 RX9D 0000 -00x 0000 -00x 0000 0000 0000 0000 0000 0000 0000 0000 TX9D 0000 -010 0000 -010 0000 0000 0000 0000 2001 Microchip Technology Inc. ...

Page 105

... RX9 ADDEN RX9 ADDEN RSR<8> 2001 Microchip Technology Inc. • Flag bit RCIF will be set when reception is com- plete, and an interrupt will be generated if enable bit RCIE was set. • Read the RCSTA register to get the ninth bit and determine if any error occurred during reception. ...

Page 106

... Word 1 RCREG Value on: Value on Bit 0 POR, all other BOR RESETS R0IF 0000 000x 0000 000u 0000 0000 RX9D 0000 000x 0000 000x 0000 0000 0000 0000 0000 0000 TX9D 0000 -010 0000 -010 0000 0000 0000 0000 2001 Microchip Technology Inc. ...

Page 107

... TSR register is empty transfer to the TXREG register will result in an immediate transfer to TSR, resulting in an empty TXREG. Back-to-back transfers are possible. 2001 Microchip Technology Inc. PIC16F87X Clearing enable bit TXEN during a transmission will cause the transmission to be aborted and will reset the transmitter ...

Page 108

... RX9D 0000 -00x 0000 -00x 0000 0000 0000 0000 0000 0000 0000 0000 TX9D 0000 -010 0000 -010 0000 0000 0000 0000 bit 1 bit 7 Word 2 ’1’ bit6 bit7 2001 Microchip Technology Inc. ...

Page 109

... Legend unknown unimplemented, read as '0'. Shaded cells are not used for synchronous master reception. Note 1: Bits PSPIE and PSPIF are reserved on PIC16F873/876 devices; always maintain these bits clear. 2001 Microchip Technology Inc. receive bit is buffered the same way as the receive data. Reading the RCREG register will load bit RX9D ...

Page 110

... Value on all Value on: Bit 0 other POR, BOR RESETS R0IF 0000 000x 0000 000u 0000 0000 RX9D 0000 000x 0000 000x 0000 0000 0000 0000 0000 0000 TX9D 0000 -010 0000 -010 0000 0000 0000 0000 2001 Microchip Technology Inc. ...

Page 111

... Baud Rate Generator Register Legend unknown unimplemented, read as '0'. Shaded cells are not used for synchronous slave reception. Note 1: Bits PSPIE and PSPIF are reserved on PIC16F873/876 devices, always maintain these bits clear. 2001 Microchip Technology Inc interrupts are desired, set enable bit RCIE. ...

Page 112

... PIC16F87X NOTES: DS30292C-page 110 2001 Microchip Technology Inc. ...

Page 113

... A/D converter module is shut-off and consumes no operating current Note 1: These channels are not available on PIC16F873/876 devices. Legend Readable bit - n = Value at POR 2001 Microchip Technology Inc. The A/D module has four registers. These registers are: • A/D Result High Register (ADRESH) • A/D Result Low Register (ADRESL) • ...

Page 114

... RA3 RA3 RA3 RA2 6 6 RA3 V 5 RA3 RA2 4 RA3 RA2 3 RA3 RA2 2 1 RA3 RA2 1 Bit is unknown 2001 Microchip Technology Inc. / ...

Page 115

... V REF (Reference Voltage) V REF (Reference Voltage) Note 1: Not available on PIC16F873/876 devices. 2001 Microchip Technology Inc. 3. Wait the required acquisition time. 4. Start conversion: • Set GO/DONE bit (ADCON0) 5. Wait for A/D conversion to complete, by either: • Polling for the GO/DONE bit to be cleared (with interrupts enabled); OR • ...

Page 116

... Sampling Switch LEAKAGE V = 0.6V T ± 500 the minimum acquisition time, , see ACQ Mid-Range Reference Manual SS C HOLD = DAC capacitance = 120 Sampling Switch (k ) 2001 Microchip Technology Inc. ...

Page 117

... Analog levels on any pin that is defined as a digital input (including the AN7:AN0 pins), may cause the input buffer to con- sume current that is out of the device specifications. 2001 Microchip Technology Inc. For correct A/D conversions, the A/D conversion clock (T ) must be selected to ensure a minimum ...

Page 118

... A/D result will not overwrite these locations (A/D dis- able), these registers may be used as two general purpose 8-bit registers. 10-bit Result 0 7 ADRESH 10-bit Result wait, acquisition AD and a maximum ADFM = 0000 00 ADRESL Left Justified 2001 Microchip Technology Inc. ...

Page 119

... Legend unknown unchanged unimplemented, read as '0'. Shaded cells are not used for A/D conversion. Note 1: These registers/bits are not available on the 28-pin devices. 2001 Microchip Technology Inc. Turning off the A/D places the A/D module in its lowest current consumption state. Note: For the A/D module to operate in SLEEP, the A/D clock source must be set to RC (ADCS1:ADCS0 = 11) ...

Page 120

... PIC16F87X NOTES: DS30292C-page 118 2001 Microchip Technology Inc. ...

Page 121

... It is designed to keep the part in RESET while the power supply stabilizes. With these two timers on-chip, most applications need no external RESET circuitry. 2001 Microchip Technology Inc. PIC16F87X SLEEP mode is designed to offer a very low current Power-down mode. The user can wake-up from SLEEP through external RESET, Watchdog Timer Wake-up, or through an interrupt ...

Page 122

... DEBUG: In-Circuit Debugger Mode 1 = In-Circuit Debugger disabled, RB6 and RB7 are general purpose I/O pins 0 = In-Circuit Debugger enabled, RB6 and RB7 are dedicated to the debugger ...

Page 123

... C2 Note 1: See Table 12-1 and Table 12-2 for recom- mended values of C1 and C2 series resistor (R ) may be required for AT s strip cut crystals varies with the crystal chosen. 2001 Microchip Technology Inc. FIGURE 12-2: Clock from Ext. System TABLE 12-1: The Mode XT HS These values are for design guidance only ...

Page 124

... V DD ± 20 PPM R EXT ± 20 PPM ± 50 PPM C EXT ± 50 PPM V SS ± 30 PPM F ± 30 PPM Recommended values: ) values, and the operat- EXT RC OSCILLATOR MODE Internal OSC1 Clock PIC16F87X OSC2/CLKOUT /4 OSC 100 k EXT C > 20pF EXT 2001 Microchip Technology Inc. ...

Page 125

... On-chip 10-bit Ripple Counter RC OSC Note 1: This is a separate oscillator from the RC oscillator of the CLKIN pin. 2001 Microchip Technology Inc. PIC16F87X SLEEP, and Brown-out Reset (BOR). They are not affected by a WDT Wake-up, which is viewed as the resumption of normal operation. The TO and PD bits are set or cleared differently in different RESET situa- tions as indicated in Table 12-4 ...

Page 126

... OSC OSC — falls below V DD BOR BOR falls below V for less DD BOR rises above V . The DD BOR should fall DD , the Brown-out Reset pro- PWRT rises above V with the DD BOR Wake-up from SLEEP 1024T OSC OSC — 2001 Microchip Technology Inc. ...

Page 127

... Brown-out Reset Interrupt wake-up from SLEEP Legend unchanged unknown unimplemented bit, read as '0' Note 1: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h). 2001 Microchip Technology Inc. PIC16F87X Program STATUS Counter ...

Page 128

... Microchip Technology Inc. ...

Page 129

... See Table 12-5 for RESET value for specific condition. FIGURE 12-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED MCLR INTERNAL POR PWRT TIME-OUT OST TIME-OUT INTERNAL RESET 2001 Microchip Technology Inc. Power-on Reset, MCLR Resets, Brown-out Reset WDT Reset 877 -r-0 0--0 -r-0 0--0 877 ---- --qq ---- --uu ...

Page 130

... PWRT TIME-OUT OST TIME-OUT INTERNAL RESET FIGURE 12-8: SLOW RISE TIME (MCLR TIED MCLR INTERNAL POR PWRT TIME-OUT OST TIME-OUT INTERNAL RESET DS30292C-page 128 T PWRT T PWRT ) PWRT T OST ): CASE OST ): CASE OST 2001 Microchip Technology Inc. ...

Page 131

... Device T0IF INTF RBIF PSPIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF EEIF BCLIF CCP2IF PIC16F876/873 Yes Yes Yes — PIC16F877/874 Yes Yes Yes Yes 2001 Microchip Technology Inc. The RB0/INT pin interrupt, the RB port change inter- rupt, and the TMR0 overflow interrupt flags are con- tained in the INTCON register ...

Page 132

... PIC16F876/877 devices, temporary holding regis- ters W_TEMP, STATUS_TEMP, and PCLATH_TEMP should be placed in here. These 16 locations don’t require banking and therefore, make it easier for con- text save and restore. The same code shown in Example 12-1 can be used. 2001 Microchip Technology Inc. ...

Page 133

... RBPU Legend: Shaded cells are not used by the Watchdog Timer. Note 1: See Register 12-1 for operation of these bits. 2001 Microchip Technology Inc. WDT time-out period values may be found in the Elec- trical Specifications section under parameter #31. Val- ues for the WDT prescaler (actually a postscaler, but shared with the Timer0 prescaler) may be assigned using the OPTION_REG register ...

Page 134

... SLEEP instruction completes. To determine whether a SLEEP instruction executed, test the PD bit. If the PD bit is set, the SLEEP instruction was executed as a NOP. To ensure that the WDT is cleared, a CLRWDT instruc- tion should be executed before a SLEEP instruction. 2001 Microchip Technology Inc. ...

Page 135

... In-Circuit Serial Programming connections to MCLR/V RB7 and RB6. This will interface to the In-Circuit Debugger module available from Microchip, or one of the third party development tool companies. 2001 Microchip Technology Inc (2) T OST ...

Page 136

... For all other cases of low voltage ICSP, the part may be programmed at the normal oper- ating voltage. This means calibration values, unique user IDs, or user code can be reprogrammed or added. to the IHH on IHH 2001 Microchip Technology Inc. ...

Page 137

... Byte-oriented operations • Bit-oriented operations • Literal and control operations 2001 Microchip Technology Inc. PIC16F87X All instructions are executed within one single instruc- tion cycle, unless a conditional test is true or the pro- gram counter is changed as a result of an instruction. ...

Page 138

... TO,PD 0000 0110 0100 1kkk kkkk kkkk Z 1000 kkkk kkkk 00xx kkkk kkkk 0000 0000 1001 01xx kkkk kkkk 0000 0000 1000 TO,PD 0000 0110 0011 C,DC,Z 110x kkkk kkkk Z 1010 kkkk kkkk Mid-Range MCU ™ 2001 Microchip Technology Inc. ...

Page 139

... Operation: (W) .AND. (f) (destination) Status Affected: Z Description: AND the W register with register 'f the result is stored in the W register the result is stored back in register 'f'. 2001 Microchip Technology Inc. PIC16F87X BCF Bit Clear f Syntax: [label] BCF f,b Operands 127 ...

Page 140

... W. If ’d’ the result is stored back in register ’f’. Decrement f [label] DECF f 127 d [0,1] ( (destination) Z Decrement register ’f’. If ’d’ the result is stored in the W register. If ’d’ the result is stored back in register ’f’. 2001 Microchip Technology Inc. ...

Page 141

... Status Affected: Z Description: The contents of register ’f’ are incremented. If ’d’ the result is placed in the W register. If ’d’ the result is placed back in register ’f’. 2001 Microchip Technology Inc. PIC16F87X INCFSZ Increment f, Skip if 0 Syntax: [ label ] INCFSZ f,d Operands: ...

Page 142

... GIE None Return with Literal label ] RETLW 255 k (W); TOS PC None The W register is loaded with the eight bit literal 'k'. The program counter is loaded from the top of the stack (the return address). This is a two-cycle instruction. 2001 Microchip Technology Inc. ...

Page 143

... The contents of register ’f’ are rotated one bit to the right through the Carry Flag. If ’d’ the result is placed in the W register. If ’d’ the result is placed back in register ’f’. C Register f 2001 Microchip Technology Inc. PIC16F87X SLEEP Syntax: [ label ] SLEEP Operands: None Operation: ...

Page 144

... XORWF Exclusive OR W with f Syntax: [label] XORWF Operands 127 d [0,1] Operation: (W) .XOR. (f) destination) Status Affected: Z Description: Exclusive OR the contents of the W register with register 'f the result is stored in the W register the result is stored back in register 'f'. 2001 Microchip Technology Inc. f,d ...

Page 145

... A project manager • Customizable toolbar and key mapping • A status bar • On-line help 2001 Microchip Technology Inc. The MPLAB IDE allows you to: • Edit your source files (either assembly or ‘C’) • One touch assemble (or compile) and download to PICmicro emulator and simulator tools (auto- matically updates all project information) • ...

Page 146

... PIC16C7X and PIC16CXXX families of 8-bit One- Time-Programmable (OTP) microcontrollers. The mod- ular system can support different subsets of PIC16C5X or PIC16CXXX products through the use of inter- changeable personality modules, or daughter boards. The emulator is capable of emulating without target application circuitry being present. 2001 Microchip Technology Inc. ...

Page 147

... PIC16C92X PIC17C76X, may be supported with an adapter socket. The PICSTART Plus development programmer is CE compliant. 2001 Microchip Technology Inc. 14.11 PICDEM 1 Low Cost PICmicro Demonstration Board The PICDEM 1 demonstration board is a simple board which demonstrates the capabilities of several of Microchip’s microcontrollers. The microcontrollers sup- ...

Page 148

... EE OQ Programming Tools K L evaluation and programming tools support EE OQ Microchip’s HCS Secure Data Products. The HCS eval- uation kit includes a LCD display to show changing codes, a decoder to decode transmissions and a pro- gramming interface to program test transmitters. 2001 Microchip Technology Inc. ...

Page 149

... PIC16C6X á á á á PIC16C5X á á á PIC14000 á á á á PIC12CXXX Tools Software Emulators 2001 Microchip Technology Inc. á á á á á á á á á á á á á á á á á á ...

Page 150

... PIC16F87X NOTES: DS30292C-page 148 2001 Microchip Technology Inc. ...

Page 151

... This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. 2001 Microchip Technology Inc. (except V , MCLR. and RA4) ....................................... -0 (Note 2) ...

Page 152

... V 5.5 V 5.0 V 4.5 V 4.0 V 3.5 V 3.0 V 2 (6.0 MHz/V) (V MAX Note the minimum voltage of the PICmicro DDAPPMIN Note 2: F has a maximum frequency of 10MHz. MAX DS30292C-page 150 16 MHz Frequency 4 MHz 10 MHz Frequency - 2 MHz DDAPPMIN ® 20 MHz device in the application. 2001 Microchip Technology Inc. ...

Page 153

... FIGURE 15-3: PIC16F87X-04 VOLTAGE-FREQUENCY GRAPH (ALL TEMPERATURE RANGES) 6.0 V 5.5 V 5.0 V 4.5 V 4.0 V 3.5 V 3.0 V 2.5 V 2.0 V FIGURE 15-4: PIC16F87X-10 VOLTAGE-FREQUENCY GRAPH (EXTENDED TEMPERATURE RANGE ONLY) 6.0 V 5.5 V 5.0 V 4.5 V 4.0 V 3.5 V 3.0 V 2.5 V 2.0 V 2001 Microchip Technology Inc. PIC16F87X-04 4 MHz Frequency PIC16F87X-10 10 MHz Frequency PIC16F87X DS30292C-page 151 ...

Page 154

... A Conditions LP, XT, RC osc configuration ( MHz) LP, XT, RC osc configuration HS osc configuration (7) BOR enabled MHz MAX See section on Power-on Reset for details details BODEN bit in configuration word enabled ; DD and voltage trip point is reached. BOR 2001 Microchip Technology Inc. ...

Page 155

... This current should be added to the base When BOR is enabled, the device will operate correctly until the V 2001 Microchip Technology Inc. PIC16F873/874/876/877-04 (Commercial, Industrial) PIC16F873/874/876/877-20 (Commercial, Industrial) PIC16LF873/874/876/877-04 (Commercial, Industrial) (Continued) Standard Operating Conditions (unless otherwise stated) Operating temperature -40° ...

Page 156

... 4.0V, WDT enabled 3.0V, WDT enabled + 4.0V, WDT enabled 3.0V, WDT enabled 4.0V, WDT enabled +85 C BOR enabled 5. and voltage trip point is reached. BOR 2001 Microchip Technology Inc. ...

Page 157

... The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Negative current is defined as current sourced by the pin. 2001 Microchip Technology Inc. Standard Operating Conditions (unless otherwise stated) Operating temperature -40° ...

Page 158

... MIN — 1000 — — E — 5 min operating voltage MIN MIN V — 5.5 V Using EECON to read/write, MIN V = min. operating voltage MIN — 2001 Microchip Technology Inc. +85°C for industrial +70°C for commercial Conditions = 4.5V 4.5V 4.5V 4.5V, DD ...

Page 159

... This current should be added to the base When BOR is enabled, the device will operate correctly until the V 2001 Microchip Technology Inc. PIC16F873/874/876/877-04 (Extended) PIC16F873/874/876/877-10 (Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C Min Typ† ...

Page 160

... R in kOhm. DD EXT EXT measurement. T +125°C A Conditions RC osc configurations MHz 5.5V OSC DD HS osc configuration MHz 5.5V OSC DD BOR enabled 5. 4.0V, WDT enabled 4.0V, WDT disabled DD BOR enabled 5. and voltage trip point is reached. BOR 2001 Microchip Technology Inc. ...

Page 161

... The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Negative current is defined as current sourced by the pin. 2001 Microchip Technology Inc. Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C Operating voltage V ...

Page 162

... V Using EECON to read/write MIN V MIN — 1000 — — E — 5 MIN MIN V — 5.5 V Using EECON to read/write, MIN V MIN — 2001 Microchip Technology Inc. Conditions = min. operating voltage = min operating voltage = min. operating voltage ...

Page 163

... Load Condition 1 Pin R = 464 for all pins except OSC2, but including PORTD and PORTE outputs as ports for OSC2 output Note: PORTD and PORTE are not implemented on PIC16F873/876 devices. 2001 Microchip Technology Inc specifications only ...

Page 164

... HS osc mode (-20 osc mode ns RC osc mode ns XT osc mode ns HS osc mode (-04 osc mode (-10 osc mode (-20 osc mode 4/F CY OSC ns XT oscillator s LP oscillator ns HS oscillator ns XT oscillator ns LP oscillator ns HS oscillator 2001 Microchip Technology Inc. ...

Page 165

... Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. †† These parameters are asynchronous events not related to any internal clock edges. Note 1: Measurements are taken in RC mode where CLKOUT output 2001 Microchip Technology Inc ...

Page 166

... — 1024 T — — T OSC 28 72 132 ms V — — 2.1 s 100 — — 2001 Microchip Technology Inc. 34 Conditions = 5V, -40°C to +85° 5V, -40°C to +85° OSC1 period OSC = 5V, -40°C to +85° (D005) DD BOR ...

Page 167

... TCKEZtmr1 Delay from external clock edge to timer increment * These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. 2001 Microchip Technology Inc. PIC16F87X ...

Page 168

... Extended(LF) — Standard(F) — Extended(LF) — Typ† Max Units Conditions — — ns — — ns — — ns — — ns — — ns — — ns — — prescale value ( 16 2001 Microchip Technology Inc. ...

Page 169

... data–out invalid * These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. 2001 Microchip Technology Inc Characteristic Min Typ† Max Units 20 ...

Page 170

... SPI MASTER MODE TIMING (CKE = 1, SMP = SCK (CKP = SCK (CKP = 1) SDO MSb SDI MSb IN 74 Note: Refer to Figure 15-5 for load conditions. DS30292C-page 168 MSb BIT6 - - - - - -1 75, 76 BIT6 - - - - BIT6 - - - - - -1 LSb 75, 76 BIT6 - - - -1 LSb LSb LSb 2001 Microchip Technology Inc. ...

Page 171

... SPI SLAVE MODE TIMING (CKE = SCK (CKP = 0) 71 SCK (CKP = 1) MSb SDO SDI SDI MSb IN 74 Note: Refer to Figure 15-5 for load conditions. 2001 Microchip Technology Inc MSb BIT6 - - - - - -1 75, 76 MSb IN BIT6 - - - - BIT6 - - - - - -1 LSb 75, 76 BIT6 - - - -1 LSb IN ...

Page 172

... Max Units Conditions — — ns — — ns — — ns — — ns — — — — — 145 — — ns — — — STOP Condition 2001 Microchip Technology Inc. ...

Page 173

... FIGURE 15-18 BUS DATA TIMING 103 SCL 90 91 SDA In 109 SDA Out Note: Refer to Figure 15-5 for load conditions. 2001 Microchip Technology Inc. Min Typ Max Units 100 kHz mode 4700 — — ns 400 kHz mode 600 — — 100 kHz mode 4000 — ...

Page 174

... Only relevant for Repeated START condition s s After this period, the first clock pulse is generated (Note (Note Time the bus must be free before a new transmission s can start pF C bus system, but the requirement that 2001 Microchip Technology Inc. ...

Page 175

... Data setup before CK time) 126 TckL2dtl Data hold after CK † Data in “Typ” column unless otherwise stated. These parameters are for design guidance only and are not tested. 2001 Microchip Technology Inc. 121 Characteristic Min Standard(F) Extended(LF) Standard(F) Extended(LF) ...

Page 176

... AIN REF + 0.3 V Absolute minimum electrical spec. To ensure 10-bit accuracy Average current consumption when A (Note During V acquisition. AIN Based on differential of V HOLD charge C , see AIN HOLD Section 11.1. A During A/D Conversion cycle 2001 Microchip Technology Inc. ...

Page 177

... Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. § This specification ensured by design. Note 1: ADRES register may be read on the following T 2: See Section 11.1 for minimum conditions. 2001 Microchip Technology Inc. (1) 131 130 8 7 ...

Page 178

... PIC16F87X NOTES: DS30292C-page 176 2001 Microchip Technology Inc. ...

Page 179

... Minimum: mean – 3s (-40°C to 125° 2001 Microchip Technology Inc. is standard deviation, over the whole temperature range. vs. F OVER V (HS MODE) OSC ...

Page 180

... MAXIMUM I DD 2.0 1.8 Typical: statistical mean @ 25°C 1.6 Maximum: mean + 3s (-40°C to 125°C) Minimum: mean – 3s (-40°C to 125°C) 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 0.0 0.5 1.0 DS30292C-page 178 vs. F OVER V (XT MODE) OSC DD 1.5 2.0 2.5 F (MHz) OSC vs. F OVER V (LP MODE) OSC DD 1.5 2.0 2.5 F (MHz) OSC 5.5V 5.0V 4.5V 4.0V 3.5V 3.0V 2.5V 2.0V 3.0 3.5 4.0 5.5V 5.0V 4.5V 4.0V 3.5V 3.0V 2.5V 2.0V 3.0 3.5 4.0 © 2001 Microchip Technology Inc. ...

Page 181

... Typical: statistical mean @ 25°C Maximum: mean + 3s (-40°C to 125°C) Minimum: mean – 3s (-40°C to 125°C) 100 2001 Microchip Technology Inc. vs. F OVER V (LP MODE) OSC ( vs. F OVER V (XT MODE) OSC DD ...

Page 182

... PIC16F87X FIGURE 16-7: AVERAGE F OSC (RC MODE pF 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 2.0 2.5 FIGURE 16-8: AVERAGE F OSC (RC MODE 100 pF 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 2.0 2.5 DS30292C-page 180 vs. V FOR VARIOUS VALUES 3.3k 5.1k 10k 100k 3.0 3.5 4.0 V (V) DD vs. V FOR VARIOUS VALUES 3.0 3.5 4.0 V (V) DD 4.5 5.0 5.5 3.3k 5.1k 10k 100k 4.5 5.0 5.5 © 2001 Microchip Technology Inc. ...

Page 183

... MODE, ALL PERIPHERALS DISABLED 100.00 Typical: statistical mean @ 25°C Maximum: mean + 3 (-40°C to 125°C) Minimum: mean – 3 (-40°C to 125°C) 10.00 1.00 0.10 0.01 2.0 2.5 2001 Microchip Technology Inc. vs. V FOR VARIOUS VALUES 3.0 3.5 4.0 V (V) DD Max (125C) Max (85C) Typ (25C) 3 ...

Page 184

... OVER TEMPERATURE Indeterminate State 3.5 4.0 V (V) DD vs. V OVER TEMPERATURE TMR1 DD Max Ty p (25C) 3.0 3.5 4 Typical: statistical mean @ 25°C Maximum: mean + 3s (-40°C to 125°C) Minimum: mean – 3s (-40°C to 125°C) Device in Sleep Max Sleep Typ Sleep (25C) 4.5 5.0 5.5 4.5 5.0 5.5 © 2001 Microchip Technology Inc. ...

Page 185

... FIGURE 16-14: TYPICAL, MINIMUM AND MAXIMUM WDT PERIOD vs 2.0 2.5 2001 Microchip Technology Inc. vs. V OVER TEMPERATURE WDT DD 3.0 3.5 4.0 V (V) DD Typical: statistical mean @ 25°C Maximum: mean + 3s (-40°C to 125°C) Minimum: mean – 3s (-40°C to 125°C) Max (125C) ...

Page 186

... OVER TEMPERATURE (- 125 C) DD Typical: statistical mean @ 25°C Maximum: mean + 3s (-40°C to 125°C) Minimum: mean – 3s (-40°C to 125°C) 3.0 3.5 4.0 V ( Max (-40C) Typ (25C) Min (125C (-mA) OH 4.5 5.0 5.5 (V =5V, - 125 © 2001 Microchip Technology Inc. ...

Page 187

... Maximum: mean + 3s (-40°C to 125°C) Minimum: mean – 3s (-40°C to 125°C) 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 2001 Microchip Technology Inc. vs Max (-40C) Typical: statistical mean @ 25°C Maximum: mean + 3s (-40°C to 125°C) Minimum: mean – 3s (-40°C to 125°C) Typ (25C) Min (125C ...

Page 188

... Minimum: mean – 3s (-40°C to 125°C) 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 2.0 2.5 DS30292C-page 186 vs Max (125C) Typ (25C) Min (-40C (-mA (TTL INPUT, - 125 Max (-40C) Min (125C) 3.0 3.5 4 =3V, - 125 4.5 5.0 5.5 © 2001 Microchip Technology Inc. ...

Page 189

... FIGURE 16-22: MINIMUM AND MAXIMUM V 3.5 Typical: statistical mean @ 25°C Maximum: mean + 3s (-40°C to 125°C) 3.0 Minimum: mean – 3s (-40°C to 125°C) 2.5 2.0 1.5 1.0 0.5 0.0 2.0 2.5 2001 Microchip Technology Inc. vs. V (ST INPUT, - 125 3.0 3.5 4 INPUT, - 125 3.0 3.5 4.0 V (V) DD PIC16F87X ...

Page 190

... PIC16F87X NOTES: DS30292C-page 188 © 2001 Microchip Technology Inc. ...

Page 191

... Standard OTP marking consists of Microchip part number, year code, week code, facility code, mask rev#, and assembly code. For OTP marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price. 2001 Microchip Technology Inc. PIC16F87X Example ...

Page 192

... PDIP XXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXX YYWWNNN 44-Lead TQFP XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN 44-Lead MQFP XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN 44-Lead PLCC XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN DS30292C-page 190 Example PIC16F877-04/P 0112SAA Example PIC16F877 -04/PT 0111HAT Example PIC16F877 -20/PQ 0104SAT Example PIC16F877 -20/L 0103SAT 2001 Microchip Technology Inc. ...

Page 193

... Mold Draft Angle Bottom * Controlling Parameter § Significant Characteristic Notes: Dimension D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MO-095 Drawing No. C04-070 2001 Microchip Technology Inc Units INCHES* MIN NOM ...

Page 194

... E .394 .407 .420 E1 .288 .295 .299 D .695 .704 .712 h .010 .020 .029 L .016 .033 .050 .009 .011 .013 B .014 .017 .020 MILLIMETERS MIN NOM MAX 28 1.27 2.36 2.50 2.64 2.24 2.31 2.39 0.10 0.20 0.30 10.01 10.34 10.67 7.32 7.49 7.59 17.65 17.87 18.08 0.25 0.50 0.74 0.41 0.84 1. 0.23 0.28 0.33 0.36 0.42 0. 2001 Microchip Technology Inc. ...

Page 195

... Mold Draft Angle Bottom * Controlling Parameter § Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MO-011 Drawing No. C04-016 2001 Microchip Technology Inc Units INCHES* MIN ...

Page 196

... E .463 .472 .482 D .463 .472 .482 E1 .390 .394 .398 D1 .390 .394 .398 c .004 .006 .008 B .012 .015 .017 CH .025 .035 .045 MILLIMETERS* MIN NOM MAX 44 0.80 11 1.00 1.10 1.20 0.95 1.00 1.05 0.05 0.10 0.15 0.45 0.60 0.75 1.00 0 3.5 7 11.75 12.00 12.25 11.75 12.00 12.25 9.90 10.00 10.10 9.90 10.00 10.10 0.09 0.15 0.20 0.30 0.38 0.44 0.64 0.89 1. 2001 Microchip Technology Inc. ...

Page 197

... Mold Draft Angle Bottom * Controlling Parameter § Significant Characteristic Notes: Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-022 Drawing No. C04-071 2001 Microchip Technology Inc ...

Page 198

... E1 .650 .653 .656 D1 .650 .653 .656 E2 .590 .620 .630 D2 .590 .620 .630 c .008 .011 .013 B1 .026 .029 .032 B .013 .020 .021 MILLIMETERS MIN NOM MAX 44 1.27 11 4.19 4.39 4.57 3.68 3.87 4.06 0.51 0.71 0.89 0.61 0.74 0.86 1.02 1.14 1.27 0.00 0.13 0.25 17.40 17.53 17.65 17.40 17.53 17.65 16.51 16.59 16.66 16.51 16.59 16.66 14.99 15.75 16.00 14.99 15.75 16.00 0.20 0.27 0.33 0.66 0.74 0.81 0.33 0.51 0. 2001 Microchip Technology Inc. ...

Page 199

... Microchip Technology Inc. PIC16F87X APPENDIX B: DEVICE DIFFERENCES The differences between the devices in this data sheet are listed in Table B-1. TABLE B-1: DEVICE DIFFERENCES Difference PIC16F876/873 PIC16F877/874 A/D 5 channels, 10-bits Parallel no Slave Port Packages 28-pin PDIP, 28-pin windowed CERDIP, 28-pin SOIC DS30292C-page 197 ...

Page 200

... Memory EPROM RAM 192, 368 bytes EEPROM data None Other DS30292C-page 198 PIC16F87X 28/ PSP, USART, 2 SSP (SPI Master/Slave) 20 MHz 2.0V - 5.5V 10-bit 2 4K, 8K FLASH 192, 368 bytes 128, 256 bytes In-Circuit Debugger, Low Voltage Programming 2001 Microchip Technology Inc. ...

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