TSC80C31-12CA ATMEL Corporation, TSC80C31-12CA Datasheet
TSC80C31-12CA
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TSC80C31-12CA Summary of contents
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... Description TS80C31X2 is high performance CMOS and ROMless versions of the 80C51 CMOS single chip 8-bit microcontroller. The TS80C31X2 retains all features of the TSC80C31 with 128 bytes of internal RAM, a 5-source, 4 priority level interrupt system, an on-chip oscilator and two timer/counters. In addition, the TS80C31X2 has a dual data pointer, a more versatile serial channel that facilitates multiprocessor communication (EUART) and a X2 speed improvement mechanism ...
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Block Diagram XTAL1 XTAL2 ALE/ PROG PSEN EA (1) RD (1) WR AT/TS80C31X2 2 (1) (1) RAM EUART 128x8 C51 CORE IB-bus CPU Timer 0 INT Parallel I/O Ports & Ext. Bus Timer 1 Ctrl Port 0Port 1 Port ...
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SFR Mapping The Special Function Registers (SFRs) of the TS80C31X2 fall into the following categories: • C51 core registers: ACC, B, DPH, DPL, PSW, SP, AUXR1 • I/O port registers: P0, P1, P2, P3 • Timer registers: TCON, TH0, ...
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Pin Configuration P1 P1.1 / T2EX 38 P1 P1.7 RST 9 32 P3.0/RxD 10 31 PDIL/ P3.1/TxD 30 ...
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Pin Number Mnemonic DIL LCC Vss1 39- P0.0-P0.7 43-36 32 P1.0-P1.7 1-8 2-9 21- P2.0-P2.7 24-31 28 10- P3.0-P3.7 11, 17 13- ...
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XTAL1 19 21 XTAL2 18 20 AT/TS80C31X2 External Access Enable: EA must be externally held low to enable the device to fetch code from external program memory locations Crystal 1: Input to ...
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TS80C31X2 Enhanced Features In comparison to the original 80C31, the TS80C31X2 implements some new features, which are : • The X2 option. • The Dual Data Pointer. • The 4 level interrupt priority system. • The power-off flag. • ...
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Figure 6-2. Mode Switching Waveforms XTAL1 XTAL1:2 X2 bit CPU clock STD Mode The X2 bit in the CKCON register (See Table 6-1.) allows to switch from 12 clock cycles per instruction to 6 clock cycles and vice versa. At ...
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Dual Data Pointer Register Ddptr The additional data pointer can be used to speed up code execution and reduce code size in a number of ways. The dual DPTR structure is a way by which the chip will specify ...
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Application Software can take advantage of the additional data pointers to both increase speed and reduce code size, for example, block operations (copy, compare, search ...) are well served by using one data pointer as a ’source’ pointer and ...
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TS80C31X2 Serial I/O Port The serial I/O port in the TS80C31X2 is compatible with the serial I/O port in the 80C31. It provides both synchronous and asynchronous communication modes. It operates as an Uni- versal Asynchronous Receiver and Transmitter ...
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Figure 9-3. UART Timings in Modes 2 and 3 SMOD0=0 SMOD0=1 SMOD0=1 9.2 Automatic Address Recognition The automatic address recognition feature is enabled when the multiprocessor communication feature is enabled (SM2 bit in SCON register is set). Implemented in hardware, ...
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Slave C: The SADEN byte is selected so that each slave may be addressed separately. For slave A, bit 0 (the LSB don’t-care bit; for slaves B and C, bit communicate with slave ...
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Table 9-2. SADDR - Slave Address Register (A9h Reset Value = 0000 0000b Not bit addressable AT/TS80C31X2 4428E–8051–02/08 ...
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Table 9-3. SCON Register -- SCON - Serial Control Register (98h FE/SM0 SM1 Bit Bit Number Mnemonic Description Framing Error bit (SMOD0=1) Clear to reset the error state, not cleared by a valid stop bit Set ...
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Table 9-4. PCON Register -- PCON - Power Control Register (87h SMOD1 SMOD0 Bit Bit Number Mnemonic Description Serial port Mode bit 1 7 SMOD1 Set to select double baud rate in mode Serial ...
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Interrupt System The TS80C31X2 has a total of 5 interrupt vectors: two external interrupts (INT0 and INT1), two timer interrupts (timers 0 and 1) and the serial port interrupt. These interrupts are shown in Fig- ure 10-1. Figure 10-1. ...
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A low-priority interrupt can be interrupted by a high priority interrupt, but not by another low-prior- ity interrupt. A high-priority interrupt can’t be interrupted by any other interrupt source. If two interrupt requests of different priority levels are received simultaneously, ...
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Table 10- Bit Number Reset Value = XXX0 0000b Bit addressable 4428E–8051–02/08 IP Register -- IP - Interrupt Priority Register (B8h Bit Mnemonic Reserved ...
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Table 10- Bit Number Reset Value = XXX0 0000b Not bit addressable AT/TS80C31X2 20 IPH Register -- IPH - Interrupt Priority High Register (B7h PSH ...
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Idle mode An instruction that sets PCON.0 causes that to be the last instruction executed before going into the Idle mode. In the Idle mode, the internal clock signal is gated off to the CPU, but not to the ...
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Figure 11-1. Power-Down Exit Waveform INT0 INT1 XTAL1 Active phase Exit from power-down by reset redefines all the SFRs, exit from power-down by external inter- rupt does no affect the SFRs. Exit from power-down by either reset or external interrupt ...
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TM 12. ONCE Mode (ON Chip Emulation) The ONCE mode facilitates testing and debugging of systems using TS80C31X2 without remov- ing the circuit from the board. The ONCE mode is invoked by driving certain pins of the TS80C31X2; the following ...
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Power-Off Flag The power-off flag allows the user to distinguish between a “cold start” reset and a “warm start” reset. A cold start reset is the one induced by V applied to the device and could be generated for ...
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Electrical Characteristics 14.1 Absolute Maximum Ratings Ambiant Temperature Under Bias commercial0°C to 70° industrial -40°C to 85°C Storage Temperature-65° 150°C Voltage on V Voltage on V Voltage on Any Pin to V Power ...
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DC Parameters for Standard Voltage T = 0°C to +70° -40°C to +85° Table 14-1. Symbol Parameter V Input Low Voltage IL V Input High Voltage except XTAL1, RST IH V Input High ...
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Symbol Parameter I Power Supply Current Maximum values (7) mode: idle 14.4 DC Parameters for Low Voltage T = 0°C to +70° -40°C to +85° Table 14-2. Symbol Parameter V Input Low ...
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Figure 14-1. I AT/TS80C31X2 0.5V; XTAL2 N.C RST = Port oscillator used.. 2. Idle I is measured with all output pins disconnected; XTAL1 driven with ...
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Reset = Vss after a high pulse during at least 24 clock cycles Figure 14-2. Operating I Figure 14-3. I Reset = Vss after a high pulse during at least 24 clock cycles Figure 14-4. I 4428E–8051–02/ ...
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Figure 14-5. Clock Signal Waveform for I 14.5 AC Parameters 14.5.1 Explanation of the AC Symbols Each timing symbol has 5 characters. The first character is always a “T” (stands for time). The other characters, depending on their positions, stand ...
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Table 14-7., Table 14-10. and Table 14-13. give the frequency derating formula of the AC parameter. To calculate each AC symbols, take the x value corresponding to the speed grade you need (- -L) and replace this value ...
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Table 14-6. -M Speed 40 MHz Symbol Min Max LHLL T 10 AVLL T 10 LLAX T 70 LLIV T 15 LLPL T 55 PLPH T 35 PLIV T 0 PXIX T 18 PXIZ T 85 ...
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External Program Memory Read Cycle ALE PSEN PORT 0 INSTR IN ADDRESS PORT 2 OR SFR-P2 Figure 14-6. External Program Memory Read Cycle Table 14-8. Symbol T RD Pulse Width RLRH T WR Pulse Width WLWH ...
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Table 14-9. Speed -M 40 MHz Symbol Min Max T 130 RLRH T 130 WLWH T 100 RLDV T 0 RHDX T 30 RHDZ T 160 LLDV T 165 AVDV T 50 100 LLWL T 75 AVWL T 10 QVWX ...
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Table 14-10. AC Parameters for a Variable Clock: derating formula Symbol Type T Min RLRH T Min WLWH T Max RLDV T Min RHDX T Max RHDZ T Max LLDV T Max AVDV T Min LLWL T Max LLWL T ...
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External Data Memory Read Cycle ALE PSEN RD PORT 0 ADDRESS PORT 2 OR SFR-P2 Figure 14-8. External Data Memory Read Cycle Table 14-11. Serial Port Timing - Shift Register Mode Symbol T XLXL T QVHX T XHQX T ...
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Table 14-13. AC Parameters for a Variable Clock: derating formula Symbol Type T Min XLXL T Min QVHX T Min XHQX T Min XHDX T Max XHDV 14.5.5 Shift Register Timing Waveforms 0 INSTRUCTION ALE CLOCK T QVXH OUTPUT DATA ...
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External Clock Drive Waveforms V 0.45 V Figure 14-10. External Clock Drive Waveforms 14.5.7 AC Testing Input/Output Waveforms V INPUT/OUTPUT Figure 14-11. AC Testing Input/Output Waveforms AC inputs during testing are driven at V measurement are made at V ...
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Figure 14-13. Clock Waveforms STATE4 INTERNAL CLOCK P1P2 XTAL2 ALE EXTERNAL PROGRAM MEMORY FETCH PSEN PCL OUT DATA P0 SAMPLE FLOAT P2 (EXT) READ CYCLE WRITE CYCLE PORT OPERATION MOV DEST P0 MOV DEST ...
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Ordering Information (3) Part Number Memory Size TS80C31X2-MCA TS80C31X2-MCB TS80C31X2-MCC TS80C31X2-MCE TS80C31X2-LCA TS80C31X2-LCB TS80C31X2-LCC TS80C31X2-LCE TS80C31X2-VCA TS80C31X2-VCB TS80C31X2-VCC TS80C31X2-VCE TS80C31X2-MIA TS80C31X2-MIB TS80C31X2-MIC TS80C31X2-MIE TS80C31X2-LIA TS80C31X2-LIB TS80C31X2-LIC TS80C31X2-LIE TS80C31X2-VIA TS80C31X2-VIB TS80C31X2-VIC TS80C31X2-VIE AT80C31X2-3CSUM ROMLess AT80C31X2-SLSUM ROMLess AT80C31X2-RLTUM ROMLess AT80C31X2-3CSUL ROMLess ...
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Part Number Memory Size AT80C31X2-3CSUV ROMLess AT80C31X2-SLSUV ROMLess AT80C31X2-RLTUV ROMLess Notes MHz in X2 Mode. 2. Tape and Reel available for SL, PQFP and RL packages MHz in X2 Mode. 4428E–8051–02/08 Temperature Supply Voltage Range ...
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... Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel’s products are not intended, authorized, or warranted for use as compo- nents in applications intended to support or sustain life. © Atmel Corporation 2008. All rights reserved. Atmel are the trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others. Atmel Operations Memory ...