W25Q80BVSNIG Winbond, W25Q80BVSNIG Datasheet
W25Q80BVSNIG
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W25Q80BVSNIG Summary of contents
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SERIAL FLASH MEMORY WITH DUAL AND QUAD SPI Publication Release Date: March 26, 2009 - 1 - Preliminary - Revision A W25Q80BV ...
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GENERAL DESCRIPTION 2. FEATURES ....................................................................................................................................... 5 3. PIN CONFIGURATION SOIC 150 / 208-MIL 4. PAD CONFIGURATION WSON 6X5-MM 5. PIN DESCRIPTION SOIC 150/208-MIL, AND WSON 6X5-MM 6. PIN CONFIGURATION SOIC 300-MIL 7. PIN DESCRIPTION SOIC 300-MIL 7.1 Package Types ...
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INSTRUCTIONS 10.2.1 Manufacturer and Device Identification 10.2.2 Instruction Set Table 1 (Erase, Program Instructions) 10.2.3 Instruction Set Table 2 (Read Instructions) 10.2.4 Instruction Set Table 3 (ID, Security Instructions) 10.2.5 Write Enable (06h) 10.2.6 Write Enable for Volatile Status ...
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Absolute Maximum Ratings 11.2 Operating Ranges 11.3 Power-up Timing and Write Inhibit Threshold 11.4 DC Electrical Characteristics 11.5 AC Measurement Conditions 11.6 AC Electrical Characteristics 11.7 AC Electrical Characteristics (cont’d) 11.8 Serial Output Timing 11.9 Input Timing ........................................................................................................................ 64 ...
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... Security Registers with OTP locks – Volatile & Non-volatile Status Register Bits Space Efficient Packaging – 8-pin SOIC 150/208-mil – 8-pad WSON 6x5-mm – 16-pin SOIC 300-mil – Contact Winbond for KGD and CSP options - 5 - W25Q80BV Publication Release Date: March 26, 2009 Preliminary - Revision A (1) ...
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PIN CONFIGURATION SOIC 150 / 208-MIL Figure 1a. W25Q80BV Pin Assignments, 8-pin SOIC 150 / 208-mil (Package Code SN & SS) 4. PAD CONFIGURATION WSON 6X5-MM Figure 1b. W25Q80BV Pad Assignments, 8-pad WSON 6x5-mm(Package Code ZP) 5. PIN DESCRIPTION ...
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PIN CONFIGURATION SOIC 300-MIL Figure 1c. W25Q80BV Pin Assignments, 16-pin SOIC 300-mil (Package Code SF) 7. PIN DESCRIPTION SOIC 300-MIL PAD NO. PAD NAME 1 /HOLD (IO3) 2 VCC 3 N/C 4 N/C 5 N/C 6 N/C 7 /CS ...
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Package Types W25Q80BV is offered in an 8-pin plastic 150-mil or 208-mil width SOIC (package code SN & SS) and 6x5-mm WSON (package code ZP) as shown in figure 1a, and 1b, respectively. The W25Q80BV is also offered in ...
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BLOCK DIAGRAM Block Segmentation Block Segmentation xxFF00h xxFF00h • • Sector 15 (4KB) Sector 15 (4KB) xxF000h xxF000h xxEF00h xxEF00h • • Sector 14 (4KB) Sector 14 (4KB) xxE000h xxE000h xxDF00h xxDF00h • • Sector 13 (4KB) Sector 13 ...
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FUNCTIONAL DESCRIPTION 9.1 SPI OPERATIONS 9.1.1 Standard SPI Instructions The W25Q80BV is accessed through an SPI compatible bus consisting of four signals: Serial Clock (CLK), Chip Select (/CS), Serial Data Input (DI) and Serial Data Output (DO). Standard SPI ...
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... Lock Down write protection until next power-up One Time Program (OTP) write protection * Note: This feature is available upon special order. Please contact Winbond for details. Upon power- power-down, the W25Q80BV will maintain a reset condition while VCC is below the threshold value (See Power-up Timing and Voltage Levels and Figure 37) ...
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CONTROL AND STATUS REGISTERS The Read Status Register-1 and Status Register-2 instructions can be used to provide status on the availability of the Flash memory array, if the device is write enabled or disabled, the state of write protection, ...
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... Note: 1. When SRP1, SRP0 = (1, 0), a power-down, power-up cycle will change SRP1, SRP0 to (0, 0) state. 2. This feature is available upon special order. Please contact Winbond for details. 10.1.8 Erase/Program Suspend Status (SUS) The Suspend Status bit is a read only bit in the status register (S15) that is set to 1 after executing a Erase/Program Suspend (75h) instruction ...
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Quad Enable (QE) The Quad Enable (QE) bit is a non-volatile read/write bit in the status register (S9) that allows Quad SPI operation. When the QE bit is set state (factory default), the /WP pin and ...
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Status Register Memory Protection (CMP = 0) (1) STATUS REGISTER SEC TB BP2 BP1 BP0 ...
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Status Register Memory Protection (CMP = 1) (1) STATUS REGISTER SEC TB BP2 BP1 BP0 ...
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... Additionally, while the memory is being programmed or erased, or when the Status Register is being written, all instructions except for Read Status Register will be ignored until the program or erase cycle has completed. 10.2.1 Manufacturer and Device Identification MANUFACTURER ID Winbond Serial Flash Device ID Instruction W25Q80BV (MF7-MF0) ...
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Instruction Set Table 1 (Erase, Program Instructions) BYTE 1 INSTRUCTION NAME (CODE) Write Enable 06h Write Enable for 50h Volatile Status Register Write Disable 04h Read Status Register-1 05h Read Status Register-2 35h Write Status Register 01h Page Program ...
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Instruction Set Table 2 (Read Instructions) BYTE 1 INSTRUCTION NAME (CODE) Read Data 03h Fast Read 0Bh Fast Read Dual Output 3Bh Fast Read Quad Output 6Bh Fast Read Dual I/O BBh Fast Read Quad I/O EBh (7) Word ...
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... Security Register 1: A23-16 = 00h; A15-8 = 10h; A7-0 = byte address Security Register 2: A23-16 = 00h; A15-8 = 20h; A7-0 = byte address Security Register 3: A23-16 = 00h; A15-8 = 30h; A7-0 = byte address Please note that Security Register 0 is Reserved by Winbond for future use recommended to use Security registers 1- 3 before using register 0 BYTE 2 ...
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Write Enable (06h) The Write Enable instruction (Figure 4) sets the Write Enable Latch (WEL) bit in the Status Register The WEL bit must be set prior to every Page Program, Quad Page Program, Sector Erase, ...
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Write Disable (04h) The Write Disable instruction (Figure 6) resets the Write Enable Latch (WEL) bit in the Status Register The Write Disable instruction is entered by driving /CS low, shifting the instruction code “04h” into ...
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Read Status Register-1 (05h) and Read Status Register-2 (35h) The Read Status Register instructions allow the 8-bit Status Registers to be read. The instruction is entered by driving /CS low and shifting the instruction code “05h” for Status Register-1 ...
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To complete the Write Status Register instruction, the /CS pin must be driven high after the eighth or sixteenth bit of data that is clocked in. If this is not done the Write Status Register instruction will not be executed. ...
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Read Data (03h) The Read Data instruction allows one or more data bytes to be sequentially read from the memory. The instruction is initiated by driving the /CS pin low and then shifting the instruction code “03h” followed by ...
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Fast Read (0Bh) The Fast Read instruction is similar to the Read Data instruction except that it can operate at the highest possible frequency of F (see AC Electrical Characteristics). This is accomplished by adding eight R “dummy” clocks ...
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Fast Read Dual Output (3Bh) The Fast Read Dual Output (3Bh) instruction is similar to the standard Fast Read (0Bh) instruction except that data is output on two pins; IO twice the rate of standard SPI devices. The Fast ...
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Fast Read Quad Output (6Bh) The Fast Read Quad Output (6Bh) instruction is similar to the Fast Read Dual Output (3Bh) instruction except that data is output on four pins executed before the device will accept the ...
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Fast Read Dual I/O (BBh) The Fast Read Dual I/O (BBh) instruction allows for improved random access while maintaining two IO pins, IO and similar to the Fast Read Dual Output (3Bh) instruction but with ...
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Figure 13b. Fast Read Dual I/O Instruction Sequence (Previous instruction set M5 W25Q80BV ...
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Fast Read Quad I/O (EBh) The Fast Read Quad I/O (EBh) instruction is similar to the Fast Read Dual I/O (BBh) instruction except that address and data bits are input and output through four pins IO clock are required ...
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Figure 14b. Fast Read Quad I/O Instruction Sequence (Previous instruction set M5-4 = 10) Fast Read Quad I/O with “8/16/32/64-Byte Wrap Around” The Fast Read Quad I/O instruction can also be used to access a specific portion within a page ...
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Word Read Quad I/O (E7h) The Word Read Quad I/O (E7h) instruction is similar to the Fast Read Quad I/O (EBh) instruction except that the lowest Address bit (A0) must equal 0 and only two Dummy clock are required ...
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Figure 15b. Word Read Quad I/O Instruction Sequence (Previous instruction set M5-4 = 10) Word Read Quad I/O with “8/16/32/64-Byte Wrap Around” The Word Read Quad I/O instruction can also be used to access a specific portion within a page ...
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Octal Word Read Quad I/O (E3h) The Octal Word Read Quad I/O (E3h) instruction is similar to the Fast Read Quad I/O (EBh) instruction except that the lower four Address bits (A0, A1, A2, A3) must equal 0. As ...
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Figure 16b. Octal Word Read Quad I/O Instruction Sequence (Previous instruction set M5 ...
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Set Burst with Wrap (77h) The Set Burst with Wrap (77h) instruction is used in conjunction with “Fast Read Quad I/O” and “Word Read Quad I/O” instructions to access a fixed length of 8/16/32/64-byte section within a 256-byte page. ...
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Continuous Read Mode Bits (M7-0) The “Continuous Read Mode” bits are used in conjunction with “Fast Read Dual I/O”, “Fast Read Quad I/O”, “Word Read Quad I/O” and “Octal Word Read Quad I/O” instructions to provide the highest random ...
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Page Program (02h) The Page Program instruction allows from one byte to 256 bytes (a page) of data to be programmed at previously erased (FFh) memory locations. A Write Enable instruction must be executed before the device will accept ...
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Quad Input Page Program (32h) The Quad Page Program instruction allows up to 256 bytes of data to be programmed at previously erased (FFh) memory locations using four pins: IO improve performance for PROM Programmer and applications that have ...
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Sector Erase (20h) The Sector Erase instruction sets all memory within a specified sector (4K-bytes) to the erased state of all 1s (FFh). A Write Enable instruction must be executed before the device will accept the Sector Erase Instruction ...
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Block Erase (52h) The Block Erase instruction sets all memory within a specified block (32K-bytes) to the erased state of all 1s (FFh). A Write Enable instruction must be executed before the device will accept the Block Erase ...
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Block Erase (D8h) The Block Erase instruction sets all memory within a specified block (64K-bytes) to the erased state of all 1s (FFh). A Write Enable instruction must be executed before the device will accept the Block Erase ...
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Chip Erase (C7h / 60h) The Chip Erase instruction sets all memory within the device to the erased state of all 1s (FFh). A Write Enable instruction must be executed before the device will accept the Chip Erase Instruction ...
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Erase / Program Suspend (75h) The Erase/Program Suspend instruction “75h”, allows the system to interrupt a Sector or Block Erase operation or a Page Program operation and then read from or program/erase data to, any other sectors or blocks. ...
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Erase / Program Resume (7Ah) The Erase/Program Resume instruction must be written to resume the Sector or Block Erase operation or the Page Program operation after an Erase/Program Suspend. After issued the BUSY bit in the Status Register will ...
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Power-down (B9h) Although the standby current during normal operation is relatively low, standby current can be further reduced with the Power-down instruction. The lower power consumption makes the Power-down instruction especially useful for battery powered applications (See ICC1 and ...
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Release Power-down / Device ID (ABh) The Release from Power-down / Device ID instruction is a multi-purpose instruction. It can be used to release the device from the power-down state, or obtain the devices electronic identification (ID) number. To ...
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Figure 28b. Release Power-down / Device ID Instruction Sequence Diagram - 49 - W25Q80BV Publication Release Date: March 26, 2009 Preliminary - Revision A ...
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... The instruction is initiated by driving the /CS pin low and shifting the instruction code “90h” followed by a 24-bit address (A23-A0) of 000000h. After which, the Manufacturer ID for Winbond (EFh) and the Device ID are shifted out on the falling edge of CLK with most significant bit (MSB) first as shown in figure 29 ...
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... Address bits two bits per clock. After which, the Manufacturer ID for Winbond (EFh) and the Device ID are shifted out 2 bits per clock on the falling edge of CLK with most significant bits (MSB) first as shown in figure 30. The Device ID values for the W25Q80BV is listed in Manufacturer and Device Identification table ...
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... Address bits four bits per clock. After which, the Manufacturer ID for Winbond (EFh) and the Device ID are shifted out four bits per clock on the falling edge of CLK with most significant bit (MSB) first as shown in figure 31 ...
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Read Unique ID Number (4Bh) The Read Unique ID Number instruction accesses a factory-set read-only 64-bit number that is unique to each W25Q80BV device. The ID number can be used in conjunction with user software methods to help prevent ...
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... The instruction is initiated by driving the /CS pin low and shifting the instruction code “9Fh”. The JEDEC assigned Manufacturer ID byte for Winbond (EFh) and two Device ID bytes, Memory Type (ID15-ID8) and Capacity (ID7-ID0) are then shifted out on the falling edge of CLK with most significant bit (MSB) first as shown in figure 33 ...
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... Security Register #1 Security Register #2 Security Register #3 * Please note that Security Register 0 is Reserved by Winbond for future use recommended to use Security registers 1- 3 before using register 0. The Erase Security Register instruction sequence is shown in figure 34. The /CS pin must be driven high after the eighth bit of the last byte has been latched. If this is not done the instruction will not be executed. ...
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... Security Register #1 Security Register #2 Security Register #3 * Please note that Security Register 0 is Reserved by Winbond for future use recommended to use Security registers 1- 3 before using register 0. The Program Security Register instruction sequence is shown in figure 35. The Security Register Lock Bits (LB3-0) in the Status Register-2 can be used to OTP protect the security registers. Once a lock bit is set to 1, the corresponding security register will be permanently locked, Program Security Register instruction to that register will be ignored (See 10 ...
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... R ADDRESS Security Register #0* Security Register #1 Security Register #2 Security Register #3 * Please note that Security Register 0 is Reserved by Winbond for future use recommended to use Security registers 1- 3 before using register 0. Instruction (48h) Instruction (48h) Figure 36. Read Security Registers Instruction Sequence A23-16 A15-12 ...
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ELECTRICAL CHARACTERISTICS 11.1 Absolute Maximum Ratings PARAMETERS Supply Voltage Voltage Applied to Any Pin Transient Voltage on any Pin Storage Temperature Lead Temperature Electrostatic Discharge Voltage Notes: 1. Specification for W25Q80BV is preliminary. See preliminary designation at the end ...
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Power-up Timing and Write Inhibit Threshold Parameter VCC (min) to /CS Low Time Delay Before Write Instruction Write Inhibit Threshold Voltage Note: 1. These parameters are characterized only. Symbol MIN t (1) VSL t (1) PUW V 1.0 (1) ...
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DC Electrical Characteristics PARAMETER SYMBOL IN (1) Input Capacitance C (1) Output Capacitance Cout Input Leakage I LI I/O Leakage I LO Standby Current Power-down Current Current Read Data / ...
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AC Measurement Conditions PARAMETER Load Capacitance Input Rise and Fall Times Input Pulse Voltages Input Timing Reference Voltages Output Timing Reference Voltages Note: 1. Output Hi-Z is defined as the point where data out is no longer driven. SYMBOL ...
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AC Electrical Characteristics DESCRIPTION Clock frequency for all instructions except Read Data instruction (03h) 2.7V-3.6V VCC & Industrial Temperature Clock frequency for all instructions except Read Data instruction (03h) 3.0V-3.6V VCC & Commercial Temperature Clock frequency for Read Data ...
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AC Electrical Characteristics ( DESCRIPTION /HOLD Active Hold Time relative to CLK /HOLD Not Active Setup Time relative to CLK /HOLD Not Active Hold Time relative to CLK /HOLD to Output Low-Z /HOLD to Output High-Z Write Protect Setup ...
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Serial Output Timing 11.9 Input Timing 11.10 Hold Timing - 64 - W25Q80BV ...
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PACKAGE SPECIFICATION 12.1 8-Pin SOIC 150-mil (Package Code SN) SYMBOL MIN A 1.47 A1 0.10 A2 --- b 0.33 C 0.19 D (3) 4.80 E 5.80 E1 (3) 3.80 e (2) L 0.40 --- Notes: 1. ...
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SOIC 208-mil (Package Code SS) SYMBOL y Notes: 1. Controlling dimensions: inches, unless otherwise specified. 2. BSC = Basic lead spacing between centers. 3. Dimensions D and ...
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WSON (Package Code ZP) SYMBOL ( ( MILLIMETERS MIN TYP. MAX 0.70 0.75 0.80 0.0276 0.00 0.02 0.05 0.0000 0.55 0.19 .0.20 0.25 0.0075 ...
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... Notes: 1. Advanced Packaging Information; please contact Winbond for the latest minimum and maximum specifications. 2. BSC = Basic lead spacing between centers. 3. Dimensions D and E1 do not include mold flash protrusions and should be measured from the bottom of the package. 4. The metal pad area on the bottom center of the package is connected to the device ground (GND pin). Avoid placement of exposed PCB vias under the pad ...
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SOIC 300-mil (Package Code SF) SYMBOL ( ( y Notes: 1. Controlling dimensions: inches, unless otherwise specified. 2. BSC = Basic lead spacing between centers. 3. Dimensions D ...
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... ORDERING INFORMATION W = Winbond 25Q = SpiFlash Serial Flash Memory with 4KB sectors, Dual/Quad I/O 80B = 8M-bit V = 2. 8-pin SOIC 150-mil SF = 16-pin SOIC 300-mil I = Industrial (-40°C to +85°C) ( Green Package (Lead-free, RoHS Compliant, Halogen-free (TBBA), Antimony-Oxide-free Green Package with Status Register Power-Down & OTP enabled ...
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... SOIC-8 208mil SF 8M-bit SOIC-16 300mil (1) ZP 8M-bit WSON-8 6x5mm Note: 1. WSON package type ZP is not used in the top side marking. PRODUCT NUMBER TOP SIDE MARKING W25Q80BVSNIG W25Q80BVSNIP W25Q80BVSSIG W25Q80BVSSIP W25Q80BVSFIG W25Q80BVSFIP W25Q80BVZPIG W25Q80BVZPIP Publication Release Date: March 26, 2009 - 71 - W25Q80BV 25Q80BVNIG 25Q80BVNIP ...
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... Winbond customers using or selling these products for use in such applications their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales ...