MC10E141FN Motorola, MC10E141FN Datasheet
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MC10E141FN
Manufacturer Part Number
MC10E141FN
Description
Manufacturer
Motorola
Datasheet
1.MC10E141FN.pdf
(4 pages)
Specifications of MC10E141FN
Case
PLCC28
Dc
97+
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MC10E141FN
Manufacturer:
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Quantity:
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Part Number:
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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
8 Bit Shift Register
performs serial/parallel in and serial/parallel out, shifting in either
direction. The eight inputs D 0 – D 7 accept parallel input data, while
DL/DR accept serial input data for left/right shifting. The Qn outputs do
not need to be terminated for the shift operation to function. To minimize
noise and power, any Q output not used should be left unterminated.
operation: Load, Hold, Shift Left, Shift Right, according to the Function
Table.
HIGH on the Master Reset (MR) pin asynchronously resets all the
registers to zero.
EXPANDED FUNCTION TABLE
7/96
Motorola, Inc. 1996
700MHz Min. Shift Frequency
8-Bit
Full-Function, Bi-Directional
Asynchronous Master Reset
Pin-Compatible with E241
Extended 100E V EE Range of – 4.2V to – 5.46V
75k Input Pulldown Resistors
The MC10E/100E141 is an 8-bit full-function shift register. The E141
The select pins, SEL0 and SEL1, select one of four modes of
Input data is accepted a set-up time before the positive clock edge. A
Function
Shift Right
Shift Left
Reset
Hold
Load
SEL1
V EE
CLK
MR
DR
D 0
D 1
* All V CC and V CCO pins are tied together on the die.
26
27
28
2
3
4
1
SEL0
DL
Pinout: 28-Lead PLCC (Top View)
D 2
25
5
X
X
X
H
X
X
X
L
DL
D 3
24
6
DR
H
X
L
X
X
X
X
X
D 7
D 4
23
7
SEL0
V CCO
H
H
H
H
L
L
L
X
D 6
22
8
Q 0
D 5
2–1
21
9
SEL1
H
H
H
H
X
L
L
L
V CCO
Q 1
20
10
MR
Q 7
Q 2
H
19
11
L
L
L
L
L
L
L
18
17
16
15
14
13
12
CLK
Q 6
Q 5
V CC
NC
V CCO
Q 4
Q 3
Z
Z
Z
Z
Z
Z
Z
X
Q0
D0
Q0
Q0
Q0
H
L
L
L
Q1
Q0
Q0
Q1
Q1
Q1
D1
L
L
FUNCTION TABLE
PIN NAMES
D 0 – D 7
DL, DR
SEL0, SEL1
CLK
Q 0 – Q 7
MR
SEL0
REV 3
H
H
L
L
Q2
D2
Q1
Q0
Q1
Q2
Q2
Q2
Pin
L
MC100E141
MC10E141
SEL1
H
H
L
L
Q3
Q2
Q1
Q2
Q3
Q3
Q3
D3
PLASTIC PACKAGE
L
8-BIT SHIFT
REGISTER
Parallel Data Inputs
Serial Data Inputs
Mode Select In Inputs
Clock
Data Outputs
Master Reset
CASE 776-02
FN SUFFIX
Load
Shift Right (D n to D n+1 )
Shift Left (D n to D n –1 )
Hold
Q4
D4
Q3
Q2
Q3
Q4
Q4
Q4
L
Function
Q5
Function
Q4
Q3
Q4
Q5
Q5
Q5
D5
L
Q6
D6
Q5
Q4
Q5
L
L
L
L
Q7
D7
Q6
Q5
H
H
H
L
L