M25P80-VMW6TP Numonyx, B.V., M25P80-VMW6TP Datasheet

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M25P80-VMW6TP

Manufacturer Part Number
M25P80-VMW6TP
Description
8 Mbit, low voltage, serial Flash memory with 75 MHz SPI bus interface
Manufacturer
Numonyx, B.V.
Datasheet

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M25P80-VMW6TP
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Features
December 2007
SPI bus compatible serial interface
75 MHz Clock rate (maximum)
2.7 V to 3.6 V single supply voltage
8 Mbit of Flash memory
Page Program (up to 256 bytes) in 0.64 ms
(typical)
Sector Erase (512 Kbit) in 0.6 s (typical)
Bulk Erase (8 Mbit) in 8 s (typical)
Hardware Write protection: protected area size
defined by three non-volatile bits (BP0, BP1
and BP2)
Deep Power-down mode 1 µA (typical)
Electronic signatures
– JEDEC Standard two-byte signature
– Unique ID code (UID) +16 bytes of CFI
– RES instruction one-byte signature (13h)
More than 100 000 Program/Erase cycles per
sector
More than 20 years’ data retention
Packages
– ECOPACK® (RoHS compliant)
(2014h)
data
for backward compatibility
8 Mbit, low voltage, serial Flash memory
Rev 16
with 75 MHz SPI bus interface
6 × 5 mm (MLP8)
VFQFPN8 (MP)
208 mils width
150 mils width
SO8W (MW)
SO8N (MN)
M25P80
www.numonyx.com
1/52
1

Related parts for M25P80-VMW6TP

M25P80-VMW6TP Summary of contents

Page 1

... More than 20 years’ data retention ■ Packages – ECOPACK® (RoHS compliant) December 2007 8 Mbit, low voltage, serial Flash memory with 75 MHz SPI bus interface VFQFPN8 (MP) 6 × (MLP8) Rev 16 M25P80 SO8W (MW) 208 mils width SO8N (MN) 150 mils width 1/52 www.numonyx.com 1 ...

Page 2

... Active Power, Standby Power and Deep Power-down modes . . . . . . . . . 13 4.5 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.6 Protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.7 Hold condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5 Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.1 Write Enable (WREN 6.2 Write Disable (WRDI 6.3 Read Identification (RDID 6.4 Read Status Register (RDSR 6.4.1 6.4.2 6.4.3 2/52 WIP bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 WEL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 BP2, BP1, BP0 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 M25P80 ...

Page 3

... M25P80 6.4.4 6.5 Write Status Register (WRSR 6.6 Read Data Bytes (READ 6.7 Read Data Bytes at Higher Speed (FAST_READ 6.8 Page Program (PP 6.9 Sector Erase (SE 6.10 Bulk Erase (BE 6.11 Deep Power-down (DP 6.12 Release from Deep Power-down and Read Electronic Signature (RES Power-up and Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 8 Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 9 Maximum rating ...

Page 4

... Table 18. SO8 wide – 8 lead Plastic Small Outline, 208 mils body width, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Table 19. SO8N – 8 lead Plastic Small Outline, 150 mils body width, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Table 20. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Table 21. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 4/52 M25P80 ...

Page 5

... M25P80 List of figures Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 2. VFQFPN and SO8 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 3. Bus Master and memory devices on the SPI bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 4. SPI modes supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 5. Hold condition activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 6. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 7. Write Enable (WREN) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 8. Write Disable (WRDI) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 9 ...

Page 6

... Description 1 Description The M25P80 Mbit (1 Mbit × 8) Serial Flash memory, with advanced write protection mechanisms, accessed by a high speed SPI-compatible bus. The memory can be programmed 1 to 256 bytes at a time, using the Page Program instruction. The memory is organized as 16 sectors, each containing 256 pages. Each page is 256 bytes wide ...

Page 7

... Figure 2. VFQFPN and SO8 connections 1. There is an exposed central pad on the underside of the VFQFPN package. This is pulled, internally and must not be allowed to be connected to any other voltage or signal line on the PCB See Package mechanical M25P80 HOLD ...

Page 8

... To start the Hold condition, the device must be selected, with Chip Select (S) driven Low. 2.6 Write Protect (W) The main purpose of this input signal is to freeze the size of the area of memory that is protected against program or erase instructions (as specified by the values in the BP2, BP1 and BP0 bits of the Status Register). 8/52 M25P80 ...

Page 9

... M25P80 2.7 V supply voltage the supply voltage. CC 2.8 V ground the reference for the V SS supply voltage. CC Signal description 9/52 ...

Page 10

... Serial Data Output (Q) line at a time, the other devices are high impedance. Resistors R (represented in that the M25P80 is not selected if the Bus Master leaves the S line in the high impedance state. As the Bus Master may enter a state where all inputs/outputs are in high impedance ...

Page 11

... M25P80 Example pF, that is R*C p Master never leaves the SPI bus in the high impedance state for a time period shorter than 5 µs. Figure 4. SPI modes supported CPOL CPHA µs <=> the application must ensure that the Bus p MSB ...

Page 12

... BE) can be achieved by not waiting for the worst case delay (t Write In Progress (WIP) bit is provided in the Status Register so that the application program can monitor its value, polling it to establish when the previous Write cycle, Program cycle or Erase cycle is complete. 12/ Page Program 6)). , M25P80 (PP), ). The BE ...

Page 13

... Protection modes The environments where non-volatile memory devices are used can be very noisy. No SPI device can operate correctly in the presence of excessive noise. To help combat this, the M25P80 boasts the following data protection mechanisms: ● Power-On Reset and an internal timer (t inadvertent changes while the power supply is outside the operating specification. ...

Page 14

... Upper quarter (four sectors 15) Upper half (eight sectors 15) All sectors (sixteen sectors 15) All sectors (sixteen sectors 15) All sectors (sixteen sectors 15) Figure 5). M25P80 Unprotected area (1) All sectors (sixteen sectors 15) Lower fifteen-sixteenths (fifteen sectors 14) Lower seven-eighths (fourteen sectors: ...

Page 15

... M25P80 Figure 5. Hold condition activation C HOLD Hold Condition (standard use) Operating features Hold Condition (non-standard use) AI02029D 15/52 ...

Page 16

... Address range F0000h E0000h D0000h C0000h B0000h A0000h 90000h 80000h 70000h 60000h 50000h 40000h 30000h 20000h 10000h 00000h M25P80 FFFFFh EFFFFh DFFFFh CFFFFh BFFFFh AFFFFh 9FFFFh 8FFFFh 7FFFFh 6FFFFh 5FFFFh 4FFFFh 3FFFFh 2FFFFh 1FFFFh 0FFFFh ...

Page 17

... M25P80 Figure 6. Block diagram HOLD W Control Logic Address Register and Counter High Voltage Generator I/O Shift Register 256 Byte Data Buffer 00000h 256 Bytes (Page Size) X Decoder Memory organization Status Register FFFFFh Size of the read-only memory area 000FFh AI04987 17/52 ...

Page 18

... Chip Select (S) being driven Low is an exact multiple of eight. All attempts to access the memory array during a Write Status Register cycle, Program cycle or Erase cycle are ignored, and the internal Write Status Register cycle, Program cycle or Erase cycle continues unaffected. 18/52 Table 4. M25P80 ...

Page 19

... M25P80 Table 4. Instruction set Instruction WREN Write Enable WRDI Write Disable (1) RDID Read Identification RDSR Read Status Register WRSR Write Status Register READ Read Data Bytes Read Data Bytes at Higher FAST_READ Speed PP Page Program SE Sector Erase BE Bulk Erase DP Deep Power-down Release from Deep Power- ...

Page 20

... Sector Erase (SE) instruction completion ● Bulk Erase (BE) instruction completion Figure 8. Write Disable (WRDI) instruction sequence 20/ Instruction D High Impedance Q (Figure 8) resets the Write Enable Latch (WEL) bit Instruction D High Impedance AI02281E AI03750D M25P80 ...

Page 21

... M25P80 6.3 Read Identification (RDID) The Read Identification (RDID) instruction allows to read the device identification data: ● Manufacturer identification (one byte) ● Device identification (two bytes) ● A Unique ID code (UID) followed by 16 bytes of CFI data The manufacturer identification is assigned by JEDEC, and has the value 20h for Numonyx. ...

Page 22

... Status Register (SRWD, BP2, BP1, BP0) become read-only bits and the Write Status Register (WRSR) instruction is no longer accepted for execution. 22/ BP2 Figure 10. BP1 BP0 WEL Block Protect bits Write Enable Latch bit Write In Progress bit Table 2) becomes M25P80 b0 WIP ...

Page 23

... M25P80 Figure 10. Read Status Register (RDSR) instruction sequence and data-out sequence High Impedance Instruction Status Register Out MSB Instructions Status Register Out MSB 7 AI02031E 23/52 ...

Page 24

... Figure 11. Write Status Register (WRSR) instruction sequence 24/52 Figure 11. Table 2. The Write Status Register (WRSR) instruction also allows Instruction 7 6 High Impedance MSB M25P80 ) is W Status Register AI02282D ...

Page 25

... M25P80 Table 7. Protection modes W SRWD signal bit Protected 1 1 Hardware 0 1 Protected 1. As defined by the values in the Block Protect (BP2, BP1, BP0) bits of the Status Register, as shown in Table 2. The protection features of the device are summarized in When the Status Register Write Disable (SRWD) bit of the Status Register is 0 (its initial ...

Page 26

... High Impedance Q 1. Address bits A23 to A20 are Don’t Care. 26/52 Figure 12 Instruction 24-Bit Address MSB Data Out MSB M25P80 Data Out 2 7 AI03748D ...

Page 27

... M25P80 6.7 Read Data Bytes at Higher Speed (FAST_READ) The device is first selected by driving Chip Select (S) Low. The instruction code for the Read Data Bytes at Higher Speed (FAST_READ) instruction is followed by a 3-byte address (A23- A0) and a dummy byte, each bit being latched-in during the rising edge of Serial Clock (C). ...

Page 28

... Write Enable Latch (WEL) bit is reset. A Page Program (PP) instruction applied to a page which is protected by the Block Protect (BP2, BP1, BP0) bits (see 28/52 Figure 14. 6)). Table 3 and Table 2) is not executed. M25P80 Table 15: AC ...

Page 29

... M25P80 Figure 14. Page Program (PP) instruction sequence MSB 1. Address bits A23 to A20 are Don’t Care Instruction 24-Bit Address MSB Data Byte 2 Data Byte 3 ...

Page 30

... D 1. Address bits A23 to A20 are Don’t Care. 30/ valid address for the Sector Erase (SE) instruction. Chip Select (S) Figure 15. Table 3 and Table 2) is not executed Instruction 23 22 MSB Bit Address AI03751D M25P80 ) is ...

Page 31

... M25P80 6.10 Bulk Erase (BE) The Bulk Erase (BE) instruction sets all bits to 1 (FFh). Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL). ...

Page 32

... Any Deep Power-down (DP) instruction, while an Erase, Program or Write cycle is in progress, is rejected without having any effects on the cycle that is in progress. Figure 17. Deep Power-down (DP) instruction sequence 32/52 Figure 17 Instruction specified CC1 CC2 before the supply current is reduced Stand-by Mode Deep Power-down Mode M25P80 AI03753D ...

Page 33

... Executing this instruction takes the device out of the Deep Power-down mode. The instruction can also be used to read, on Serial Data Output (Q), the 8-bit Electronic Signature, whose value for the M25P80 is 13h. Please note that this is not the same as, or even a subset of, the JEDEC 16-bit Electronic Signature that is read by the Read Identifier (RDID) instruction ...

Page 34

... Figure 18. Release from Deep Power-down and Read Electronic Signature (RES) instruction sequence and data-out sequence Instruction D High Impedance Q 1. The value of the 8-bit Electronic Signature, for the M25P80, is 13h. Figure 19. Release from Deep Power-down (RES) instruction sequence High Impedance Q 34/ ...

Page 35

... M25P80 7 Power-up and Power-down At Power-up and Power-down, the device must not be selected (that is Chip Select (S) must follow the voltage applied on V ● V (min) at Power-up, and then for a further delay ● Power-down SS A safe configuration is provided in To avoid data corruption and inadvertent write operations during Power-up, a Power On Reset (POR) circuit is included ...

Page 36

... Write Inhibit voltage WI 1. These parameters are characterized only. 36/52 Program, Erase and Write commands are Rejected by the device Chip selection Not Allowed of the device tPUW threshold WI Parameter tVSL Read Access allowed Device fully accessible Min. Max M25P80 time AI04009C Unit µ ...

Page 37

... M25P80 8 Initial delivery state The device is delivered with the memory array erased: all bits are set to 1 (each byte contains FFh). The Status Register contains 00h (all Status Register bits are 0). 9 Maximum rating Stressing the device above the rating listed in the absolute maximum ratings table may cause permanent damage to the device ...

Page 38

... MHz. A Min. Max. 2.7 3.6 –40 125 –40 85 Min. Max. Unit 100 000 cycles per sector 10 000 20 years Min. Max 0. 0. Input and Output 0.7V CC 0.5V CC 0.3V CC AI07455 Min. Max M25P80 Unit V °C °C Unit Unit pF pF ...

Page 39

... M25P80 Table 14. DC characteristics Symbol Parameter I Input leakage current LI I Output leakage current LO I Standby current CC1 I Deep Power-down current CC2 I Operating current (READ) CC3 I Operating current (PP) CC4 I Operating current (WRSR) CC5 I Operating current (SE) CC6 I Operating current (BE) CC7 V Input low voltage ...

Page 40

... Parameter (5) (peak to peak) (4) (peak to peak) and Table 12 (2) Min. Typ. Max. D. 0.1 0 100 100 3 3 1.8 1.3 15 M25P80 (1) Unit MHz MHz ns ns V/ns V/ μs μs μs ms ...

Page 41

... M25P80 Table 15. AC characteristics (75 MHz operation, Grade 6) (continued) 75 MHz available only for products made in T9HX technology, identified with Process digit “4” Test conditions specified in Symbol Alt. Page Program cycle time (256 byte) Page Program cycle time (n bytes, where ...

Page 42

... Table 12 Min. Typ. Max. D. 0.1 0 100 100 3 3 1.8 1.5 15 0.8 5 (7) int(n/8) × 0.025 M25P80 Unit MHz MHz ns ns V/ns V/ µs µs µ ...

Page 43

... M25P80 Table 16. AC characteristics (25 MHz operation, Grade 3) Test conditions specified in Symbol Alt. (6) t Sector Erase cycle time SE (6) t Bulk Erase cycle time BE 1. Preliminary data must be greater than or equal Value guaranteed by characterization, not 100% tested in production. 4. Expressed as a slew-rate. ...

Page 44

... DC and AC parameters Figure 23. Write Protect setup and hold timing during WRSR when SRWD = 1 W tWHSL High Impedance Q Figure 24. Hold timing HOLD 44/52 tHLCH tCHHL tCHHH tHLQZ tHHQX M25P80 tSHWL AI07439 tHHCH AI02032 ...

Page 45

... M25P80 Figure 25. Output timing S C tCLQV tCLQX tCLQX Q ADDR. D LSB IN tCH tCLQV tQLQH tQHQL DC and AC parameters tCL tSHQZ LSB OUT AI01449e 45/52 ...

Page 46

... ddd C inches Typ Min 0.0335 0.0315 0.0000 0.0256 0.0079 0.0157 0.0138 0.2362 0.2264 0.1339 0.1260 0.1969 0.1870 0.1575 0.1496 0.0500 – 0.0039 0.0000 0.0236 0.0197 M25P80 70-ME Max 0.0394 0.0020 0.0189 0.1417 0.1693 – 0.0295 12° 0.0059 0.0039 0.0020 ...

Page 47

... M25P80 Figure 27. SO8 wide – 8 lead Plastic Small Outline, 208 mils body width, package outline 1. Drawing is not to scale. 2. The ‘1’ that appears in the top view of the package shows the position of pin 1. Table 18. SO8 wide – 8 lead Plastic Small Outline, 208 mils body width, ...

Page 48

... GAUGE PLANE SO-A inches Typ Min 0.004 0.049 0.011 0.007 0.193 0.189 0.236 0.228 0.154 0.150 0.050 – 0.010 0° 0.016 0.041 M25P80 Max 0.069 0.010 0.019 0.009 0.004 0.197 0.244 0.157 – 0.020 8° 0.050 ...

Page 49

... Numonyx Sales Office. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. M25P80 (1) Part numbering – ...

Page 50

... Note on SO8 package removed below scheme. 10 SO8N package added (see Changes Page Programming, and Instruction Times (Device Grade Table 20: Ordering Figure 25: Output timing. endurance. modified and and Note 2 added below Figure Table 20: Ordering information Figure 28 and Table 19). M25P80 Page 3). on page 27. ...

Page 51

... M25P80 Table 21. Document revision history Date Revision 22-Sep-2006 12-Oct-2006 15-Dec-2006 09-Jan-2007 15-Jun-2007 10-Dec-2007 Endurance and data retention information added to Features. 50 MHz frequency added, Instruction times table removed, data appended to Table 15: AC characteristics (40 MHz operation, Grade 6) and characteristics (25MHz operation). Typical Table 15: AC characteristics (40 MHz operation, Grade 6) and added ...

Page 52

... Copies of documents which have an order number and are referenced in this document, or other Numonyx literature may be obtained by Numonyx StrataFlash is a trademark or registered trademark of Numonyx or its subsidiaries in the United States and other countries. *Other names and brands may be claimed as the property of others. 52/52 Please Read Carefully: applications. visiting Numonyx's website at http://www.numonyx.com. Copyright © 11/5/7, Numonyx, B.V., All Rights Reserved. M25P80 ...

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