M25PE20-VMP6TP Numonyx, B.V., M25PE20-VMP6TP Datasheet - Page 62

• Manufacturer Part Number: M25PE20-VMP6TP
• Description: 1 and 2 Mbit, page-erasable serial Flash memories with byte alterability, 75 MHz SPI bus, standard pinout
• Manufacturer: Numonyx, B.V.

Revision history
14
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Revision history
Table 30.
07-Dec-2004
21-Dec-2004
25-Jan-2007
10-Jul-2006
6-Oct-2005
Date
Document revision history
Version
0.1
0.2
1.0
2
3
Document written
Notes 1 and 2 removed from
S08N silhouette corrected
Added
promoted to full Datasheet.
modify
to explain optimal use of Page Write and Page Program instructions. Clock
slew rate changed from 0.03 to 0.1 V/ns. Updated
information
Document converted to the new Numonyx template.
MLP package removed, SO8N package specifications updated (see
Section 12: Package
Figure 5: SPI modes supported
t
50 MHz frequency added. VFQFPN package added (see
Package
The sectors are further divided up into subsectors (see
memory organization
Important note on page 6
devices on the SPI bus
supply voltage
modified.
Reset conditions
At power-up the WIP bit is reset and the Lock Registers are reset (see
Section 7: Power-up and
V
M25PE20 and M25PE10 products processed in T9HX process added to
datasheet:
– WP pin replaces TSL (T7X technology), see
–
– subsector protection granularity removed in T9HX process, still exists in
–
– Status Register
Small text changes.
SHQZ
IO
(W) or Top Sector Lock (TSL)
Read Lock Register
Status Register
instructions added for T9HX process
T7X process
Table 5: M25PE20 memory organization
memory organization
max changed in
moved in
Table 22: AC characteristics (33 MHz
data,
mechanical).
Section 8: Reset
scheme. Added ECOPACK® information.
Page Write (PW)
and
Figure
and
(WRSR),
BP1, BP0 bits
V
Table 15: Absolute maximum
SS
mechanical).
and
Table 26: Timings after a Reset Low
(RDLR),
29.
updated and explanatory paragraph added.
ground
updated to show subsectors
power-down).
added.
Table 6: M25PE10 memory
on page
added, Reset timings table split into
An easy way to modify
SubSector Erase (SSE)
Table 29: Ordering information
and
Write to Lock Register
added.
updated and
Changes
and
Figure 4: Bus master and memory
Page Program (PP)
1.
SRWD bit
Section 4.8: Protection modes
and
operation). Document status
Note 2
Section 2.7: Write Protect
Table 6: M25PE10
added.
Table 29: Ordering
ratings.
data,
M25PE20, M25PE10
and
added. Timing line of
organization).
(WRLR),
Table 5: M25PE20
sections updated
A fast way to
Bulk Erase (BE)
Section 12:
pulse.
scheme.
Table 25:
Write
V
CC