11274-001 AMI Semiconductor, Inc., 11274-001 Datasheet - Page 8

• Manufacturer Part Number: 11274-001
• Description: Logic and Timing, Programmable Line Lock Clock Generator IC, Tape and Reel
• Manufacturer: AMI Semiconductor, Inc.

FS6131-01
FS6131-01
FS6131-01
FS6131-01
Programmable Line Lock Clock Generator IC
Programmable Line Lock Clock Generator IC
Programmable Line Lock Clock Generator IC
Programmable Line Lock Clock Generator IC
4.5.1.2
The direction the loop has gone out-of-range can be de-
termined by clearing STAT[1] to zero and setting STAT[0]
bit to one. If the CMOS bit is set to one, the LOCK/IPRG
pin will go high if the Crystal Loop went out of range high.
If the pin goes to a logic-low, the loop went out of range
low.
The out-of-range information is also available under soft-
ware control by reading back the STAT[1] bit, which is
overwritten by the flag (high = out-of-range high, low =
out-of-range low) in this mode. The bit is set or cleared
only if the Crystal Loop loses lock (see Table 6).
4.5.1.3
The Crystal Loop is disabled by setting the XLPDEN bit
to a logic-high (1). The bit disables the charge pump cir-
cuit in the loop.
Setting the XLPDEN bit low (0) permits the crystal loop to
operate as a control loop.
4.6
If a crystal oscillator is not used, tie XIN to ground and
shut down the crystal oscillator by setting XLROM[2:0]=1.
The REF and FBK pins do not have pull-up or pull-down
current, but do have a small amount of hysteresis to re-
duce the possibility of extra edges. Signals may be AC-
coupled into these inputs with an external DC-bias circuit
to generate a DC-bias of 2.5V. Any Reference or Feed-
back signal should be square for best results, and the
signals should be rail-to-rail. Unused inputs should be
grounded to avoid unwanted signal injection.
Out-Of-Range High/Low
Crystal Loop Disable
Connecting the FS6131 to an
External Reference Frequency
8
4.7
The differential output stage supports both CMOS and
pseudo-ECL (PECL) signals. The desired output interface
is chosen via the program registers (see Table 4).
If a PECL interface is used, the transmission line is usu-
ally terminated using a Thévenin termination. The output
stage can only sink current in the PECL mode, and the
amount of sink current is set by a programming resistor
on the LOCK/IPRG pin. The ratio of IPRG current to out-
put drive current is shown in Figure 12. Source current is
provided by the pull-up resistor that is part of the
Thévenin termination.
Figure 12: IPRG to CLKP/CLKN Current
Differential Output Stage
25.0
20.0
15.0
10.0
5.0
0.0
0
CLKP/CLKN PECL Output Current (mA)
20
40
60
80