STP2003PQFP Sun Microelectronics, STP2003PQFP Datasheet

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STP2003PQFP

Manufacturer Part Number
STP2003PQFP
Description
PCI I/O Controller
Manufacturer
Sun Microelectronics
Datasheet
DATA SHEET
D
The PCIO chip is a high integration, high performance single chip IO subsystem connected to the PCI local
bus. Using a single PCI bus load it integrates high speed Ethernet and EBus2. EBus2 is a generic slave DMA
bus (pseudo-ISA bus) to which off-the-shelf peripherals are connected to implement the rest of the Sun core
IO system.
PCIO is built around an internal bus (the Channel Engine Interface). This structure is the key to the PCIOs
modularity. Above the Channel Engine Interface, the Bus Adapter connects to the PCI bus. The two identical
ports on the Channel Engine Interface are used for each of PCIO’s functional units: Ethernet and EBus2. Each
of these has its own set of control and status registers, data buffers and the core logic function
Features
The following functions are implemented with off-the-shelf devices, connecting directly to the EBus2:
Product Summary
The PCIO uses Symbios’ VS 500, CMOS 3-layer metal technology. It has 0.75 micron drawn, 0.5 micron effec-
tive gate length, and operates at 5 volts. The device is packaged in a 208 Pin PQFP. It has 157 signals and 51
VSS/VDD pads. The PCIO cell has 88k gates and 39k bits of RAM.
The operating frequency for the PCI bus, EBus2 channel engine and the DMA engine of the Ethernet channel
is 33.3 MHz. The core, Media Access Control (MAC), operates at 25 MHz.
Maximum power consumption of the PCIO is 2 watts.
• PCI Local Bus master/slave interface, compliant with PCI Local Bus Specification, Revision 2.1
• 10baseT (802.3) and 100baseT (802.30) Ethernet, using a derivative of Media Access Control (MAC), with fully buffered
• Expansion bus interface (EBus2), supporting eight external devices and four buffered slave DMA channels.
• Oscillator for 40 MHz SCSI clock, and free running 10 MHz real-time clock.
• IEEE 1149.1 JTAG compliant test architecture.
• PC87303 Super IO, integrating 82077-compatible floppy controller with DMA, parallel port, P1284-compliant, with ECP and
• Two high performance sync/async serial ports, using Siemens SAB82532, 460.8 KBaud async, 384 KBaud sync.
• Sun compatible NVRAM, MK48T59, with alarm clock interrupt for power management.
• EPROM of flash EPROM, 8-bit wide, up to 16 Mbyte, for OBP and POST code.
• CS4231 Audio CODEC.
• Access to USC and DSC control port.
• Auxiliary IO ports, for power supply control, temperature sensor, frequency calibration and other miscellaneous functions.
ESCRIPTION
transmit and receive channels; media-independent interface (MII).
EPP with DMA and two 16C550 serial controllers with 16-byte FIFOs for keyboard and mouse.
1. Although designed to the PCI 2.0 specification, the PCIO controller is compatible with the 2.1 specification as
well. However, certain 2.1 recommended features, such as pseudo-split reads and a tighter interpretation of the
initial latency rule are not implemented.
[1]
STP2003QFP
.
PCI I/O Controller
.
PCIO
August 2001
1

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STP2003PQFP Summary of contents

Page 1

DATA SHEET D ESCRIPTION The PCIO chip is a high integration, high performance single chip IO subsystem connected to the PCI local bus. Using a single PCI bus load it integrates high speed Ethernet and EBus2. EBus2 is a generic ...

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PCIO STP2003QFP PCI I/O Controller B D LOCK IAGRAM Bus Adapter • PCI bus v2.1 compliant, 33 MHz • double 64-byte write buffers • 100+ Mbytes/sec peak transfer rate Scan Control Ethernet DMA • 2 DMA Channels • 2048 byte ...

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Bus Adapter The Bus Adapter provides a bus-independent layer between the channel engines and the PCI bus. The PCI bus interface is 32-bit and 33 MHz, fully compliant with the PCI Local Bus Specification, Revision 2. mas- ter, ...

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PCIO STP2003QFP PCI I/O Controller UPA_D0(127:0+ECC) Graphics TA (15:0) Tag TD (24+3+P) Ultra SPARC-1 DA(18+16BE) SF3 SF3a D (128+16P) 512KB E$ SDB RIC Figure 2. Typical System Application P D INOUT ESCRIPTION Pin naming conventions • All pin names are ...

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TABLE 1: Signal Name Prefixes Functional Block Prefix PCI Bus pci_ Ethernet enet_ EBus2 eb_ JTAG Port jtag_ Pin Summary TABLE 2: Pin Count Summary Section Pins PCI Interface 53 Clock Oscillator 7 Ethernet Interface 20 EBus2 Interface 41 Miscellaneous ...

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PCIO STP2003QFP PCI I/O Controller Pinout by Function TABLE 3: Pinout by Function Name Pin Dir PCI Interface: 53 pins pci_ad[0] 160 BiDir pci_ad[1] 158 BiDir pci_ad[2] 157 BiDir pci_ad[3] 156 BiDir pci_ad[4] 155 BiDir pci_ad[5] 154 BiDir pci_ad[6] 153 ...

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TABLE 3: Pinout by Function (Continued) Name Pin Dir pci_c_be_l[2] 126 BiDir pci_c_be_l[3] 112 BiDir pci_clk 99 In pci_frame_l 127 BiDir pci_devsel_l 132 BiDir pci_idsel 113 BiDir pci_irdy_l 130 BiDir pci_trdy_l 128 BiDir pci_stop_l 133 BiDir pci_par 136 BiDir pci_perr_l ...

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PCIO STP2003QFP PCI I/O Controller TABLE 3: Pinout by Function (Continued) Name Pin Dir eb_cs_l[7] 172 Tri eb_d[0] 193 BiDir eb_d[1] 192 BiDir eb_d[2] 190 BiDir eb_d[3] 188 BiDir eb_d[4] 187 BiDir eb_d[5] 186 BiDir eb_d[6] 185 BiDir eb_d[7] 184 ...

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TABLE 3: Pinout by Function (Continued) Name Pin Dir enet_rxd[ enet_tx_clki 10 In enet_tx_clko 8 Tri enet_tx_col 14 In enet_tx_crs 11 In enet_tx_en 9 Tri enet_txd[0] 30 Tri enet_txd[1] 28 Tri enet_txd[2] 26 Tri enet_txd[3] 24 Tri Miscellaneous ...

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PCIO STP2003QFP PCI I/O Controller TABLE 3: Pinout by Function (Continued) Name Pin Dir SCSI Clock Oscillator: 7 pins osc_rst_l 1 In scsi_clk 83 Out scsi_oscen 82 In scsi_x1 85 In scsi_x2 86 Out clk_10m 81 Out clk_5m 79 Out ...

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TABLE 3: Pinout by Function (Continued) Name Pin Dir BSVSSIO_1 116 124 137 145 151 161 171 178 189 199 208 PCIVDDIO 91 119 143 159 VDDIO 173 191 VSSCORE 117 141 ...

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PCIO STP2003QFP PCI I/O Controller Pinout by Pin Number TABLE 4: Pinout by Pin Number Name Pin Dir osc_rst_l 1 In diag[4] 2 Out diag[3] 3 Out diag[2] 4 Out diag[1] 5 Out BSVSSIO_1 6 diag[0] 7 Out enet_tx_clko 8 ...

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TABLE 4: Pinout by Pin Number (Continued) Name Pin Dir jtag_tdo 36 Out BSINVSSIO 37 jtag_tdi 38 In VSSCORE 39 jtag_clk 40 In VDDIO 41 jtag_tms 42 In jtag_trst_l 43 In clock_stop 44 In cod_pdwn_l 45 Out BSVSSIO_1 46 tsens_cs_l ...

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PCIO STP2003QFP PCI I/O Controller TABLE 4: Pinout by Pin Number (Continued) Name Pin Dir au_cap_irq_l 72 Out eb_irq4 73 In eb_irq3 74 In eb_irq2 75 In eb_irq1 76 In eb_rdy 77 In BSVSSIO 78 clk_5m 79 Out VSSCORE 80 ...

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TABLE 4: Pinout by Pin Number (Continued) Name Pin Dir pci_ad[26] 108 BiDir BSVSSIO_1 109 pci_ad[25] 110 BiDir pci_ad[24] 111 BiDir pci_c_be_l[3] 112 BiDir pci_idsel 113 BiDir pci_ad[23] 114 BiDir pci_ad[22] 115 BiDir BSVSSIO_1 116 VSSCORE 117 pci_ad[21] 118 BiDir ...

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PCIO STP2003QFP PCI I/O Controller TABLE 4: Pinout by Pin Number (Continued) Name Pin Dir pci_ad[12] 144 BiDir BSVSSIO_1 145 pci_ad[11] 146 BiDir pci_ad[10] 147 BiDir pci_ad[9] 148 BiDir pci_ad[8] 149 BiDir pci_c_be_l[0] 150 BiDir BSVSSIO_1 151 pci_ad[7] 152 BiDir ...

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TABLE 4: Pinout by Pin Number (Continued) Name Pin Dir eb_cs_l[1] 180 Tri eb_cs_l[0] 181 Tri VSSCORE 182 BSVSSIO 183 eb_d[7] 184 BiDir eb_d[6] 185 BiDir eb_d[5] 186 BiDir eb_d[4] 187 BiDir eb_d[3] 188 BiDir BSVSSIO_1 189 eb_d[2] 190 BiDir ...

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PCIO STP2003QFP PCI I/O Controller Pinout by Pin Name TABLE 5: Pinout by Pin Name Name Pin Dir BSINVSSIO 37 BSVSSIO 131 183 78 96 BSVSSIO_1 100 109 116 12 124 137 145 151 161 171 178 189 199 20 ...

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TABLE 5: Pinout by Pin Name (Continued) Name Pin Dir VDDIO 15 173 191 VSSCORE 117 13 141 182 39 80 au_cap_irq_l 72 Out au_pb_irq_l 71 Out aux_ps_off 52 Out boot[ boot[ ...

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PCIO STP2003QFP PCI I/O Controller TABLE 5: Pinout by Pin Name (Continued) Name Pin Dir eb_cs_l[2] 179 Tri eb_cs_l[3] 177 Tri eb_cs_l[4] 176 Tri eb_cs_l[5] 175 Tri eb_cs_l[6] 174 Tri eb_cs_l[7] 172 Tri eb_d[0] 193 BiDir eb_d[1] 192 BiDir eb_d[2] ...

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TABLE 5: Pinout by Pin Name (Continued) Name Pin Dir enet_rx_er 23 In enet_rxd[ enet_rxd[ enet_rxd[ enet_rxd[ enet_tx_clki 10 In enet_tx_clko 8 Tri enet_tx_col 14 In enet_tx_crs 11 In enet_tx_en 9 Tri ...

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PCIO STP2003QFP PCI I/O Controller TABLE 5: Pinout by Pin Name (Continued) Name Pin Dir pci_ad[10] 147 BiDir pci_ad[11] 146 BiDir pci_ad[12] 144 BiDir pci_ad[13] 142 BiDir pci_ad[14] 140 BiDir pci_ad[15] 139 BiDir pci_ad[16] 125 BiDir pci_ad[17] 123 BiDir pci_ad[18] ...

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TABLE 5: Pinout by Pin Name (Continued) Name Pin Dir pci_par 136 BiDir pci_perr_l 134 BiDir pci_req_l 102 BiDir pci_rst_l 97 BiDir pci_s0_prsnt1 65 In pci_s0_prsnt2 63 In pci_s1_prsnt1 62 In pci_s1_prsnt2 61 In pci_s2_prsnt1 60 In pci_s2_prsnt2 59 In ...

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PCIO STP2003QFP PCI I/O Controller E S LECTRICAL PECIFICATIONS TABLE 6: Absolute Maximum Ratings Symbol Parameter VDD DC Power Supply Voltage Vin, Vout DC Input, Output Voltage I DC Current Drain per VDD and VSS pair Tstg Storage Temperature Tcm ...

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TABLE 8: DC Characteristics Symbol Parameter Vil Input Low Voltage TTL CMOS Vih Input High Voltage TTL CMOS Voh Output High Voltage TTL CMOS PCI (DC) Vol Output Low Voltage TTL CMOS PCI (DC) Ii Input Leakage (non PCI ...

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PCIO STP2003QFP PCI I/O Controller AC C HARACTERISTICS AC Timing Characteristics have been obtained with operating conditions exceeding the recommended limits. A 10% voltage variation, 4.5V to 5.5V, is factored into the vendors BCCOM and WCCOM timing libraries and is ...

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TABLE 11: Ethernet Timing Characteristics Symbol Parameter RX and TX Clocks T_cyc rx/tx clk Cycle Time Duty Cycle MII Interface T_su(rx) MII RX Inputs Setup Time to rx_clk T_hld(rx) MII RX Inputs Hold Time to rx_clk T_su(tx) MII TX Inputs ...

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PCIO STP2003QFP PCI I/O Controller EBus2 Timing The EBus2 is an asynchronous bus. Its timing is self regulated handshaking, having no fixed relationship to the PCIO clock. The EBus2 timing is programmable via three timing control registers in the Ebus2 ...

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EBus2 Output and Input Signals: AC Timing Characteristics Table 13 specifies the AC tming characteristics required on the EBus2 input and output signals. TABLE 13: EBus2 Timing Characteristics Symbol Parameter Tcyc EBus2 Clock Cycle Time T_high EBus2 Clock High Time ...

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PCIO STP2003QFP PCI I/O Controller M I ECHANICAL NFORMATION Package Information and Drawings PCIO is packaged in a 208-pin, molded PQFP with copper fused lead frame and heat spreader for enhanced thermal dissipation. The die attach pad is 512 x ...

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PQFP Package Dimensions 157 Pin 1 Index 208 1 0.50 Nom. 4.1 Max. 3.4 ±0.2 0.25 / 0.40 August 2001 PCI I/O Controller 30.6 ±0.2 SQ. 28.0 ±0.2 SQ. 25.35 REF. 104 53 52 0.22 ±0.05 0.10 MAX 0~7° ...

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... PCIO STP2003QFP PCI I/O Controller O I RDERING NFORMATION Part Number STP2003PQFP PCIO Controller, 208-Pin Plastic Quad Flat Pack (PQFP) 32 Description Document Part Number: 802-7836-02 August 2001 ...

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