STPCC4 STMicroelectronics, STPCC4 Datasheet - Page 28

• Manufacturer Part Number: STPCC4
• Description: STPC CONSUMER-II DATASHEET - X86 CORE PC COMPATIBLE INFORMATION APPLIANCE SYSTEM-ON-CHIP
• Manufacturer: STMicroelectronics

STRAP OPTIONS
3.1. POWER-ON STRAP REGISTER DESCRIPTIONS
3.1.1. ADPC STRAP REGISTER 0 CONFIGURATION
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Strap0
Bit Number Sampled
MD[7]
7
Bits 7-6
Bit 1-0
Bits 2
Bit 5
Bit 4
MD[6]
6
This register defaults to the values sampled on MD[7:4] pins after reset
Mnemonic
MD[4,17]
MD[7:6]
MD[44]
See Table
MD[5]
MD[4]
MD[5]
Rsv
Rsv
below
5
Release 1.5 - January 29, 2002
Access = 0022h/0023h
Description
PCICLK PLL set-up:
PCICLK PLL programming according to PCICLK frequency.
MD7 MD6
For the parts referenced STPCC4 , see section Section 3.1.1.bit 2.
For the parts referenced STPCC5, this s
Bus or ISA mode.
This strap is not readable in a register for the STPCC4 .
PCICLK division: This bit reflects the value sampled on [MD4] and is
used together with MD[17] to select the PCICLK frequency.
MD4 MD17
For the parts referenced STPCC4 These bits are reserved
Host Memory synchronization. This bit reflects the value sampled on
MD[5] and controls the MCLK/HCLK synchronization.
For the parts referenced STPCC4 These bits are reserved
For the parts referenced STPCC5.
These bits reflect the values sampled on MD[17] pin and
controls the PCI clock output in conjunction with MD[4], as
follows:
MD4 MD17
0
0
1
0 = ISA Mode
1 = Local Bus Mode
0
1
1
0: MCLK and HCLK not synchronized
1: MCLK and HCLK synchronized for improved system performance.
0
1
1
MD[4]
4
0
1
X
X
0
1
X
0
1
PCICLK frequency between 16 & 32 MHz
PCICLK frequency between 32 & 64 MHz
PCI Clock output = HCLK / 3
PCI Clock output = HCLK / 2
PCI Clock output = HCLK / 3
PCI Clock output = HCLK / 2
Reserved
PCI Clock output = HCLK / 4
PCI Clock output = HCLK / 4
Rsv
3
The value sampled on MD[7:6] controls the
See Table
below
2
trap selects betwen Local
See Table
below
1
Regoffset = 04Ah
See Table
belowl
0