MSC100ABIRM Motorola / Freescale Semiconductor, MSC100ABIRM Datasheet - Page 59

• Manufacturer Part Number: MSC100ABIRM
• Description: SC100 Application Binary Interface Reference Manual
• Manufacturer: Motorola / Freescale Semiconductor

5.1.1 SC140 Architecture
The entire memory space of the SC140 core is unified. The memory supports two parallel 64-bit data
accesses issued by the core at the same time, one 128-bit program bus, and external port (usually for DMA
accesses).
The two data busses that connect between the Data ALU register file and the memory are 64-bits wide
each. Load and Store instructions utilize the maximum width of the bus according to the application
requirement, by means of having different versions of the instructions for different bandwidth:
SC100 Application Binary Interface
•
•
•
•
•
MOVE.B loads or stores bytes (8-bit)
MOVE.W or MOVE.F loads or stores integer or fractional words (16-bit)
MOVE.2W, MOVE.2F and MOVE.L loads or stores double-integers, double-fractions and long
words respectively (32-bit)
MOVE.4W, MOVE.4F loads or stores quad-integers and quad-fractions respectively (64-bit)
MOVE.2L loads or stores double-long words (64-bit)
SC140
Core
Figure 5-2. SC140 Basic Architecture
Preliminary (April 2000)
128-bit P-BUS
64-bit XA-BUS
64-bit XB-BUS
Memory Organization
SRAM
p/data
0-ws
5-3