MSC8113 Freescale Semiconductor / Motorola, MSC8113 Datasheet - Page 21

• Manufacturer Part Number: MSC8113
• Description: Tri-Core Digital Signal Processor
• Manufacturer: Freescale Semiconductor / Motorola

2.5.5
2.5.5.1
Generally, all MSC8113 bus and system output signals are driven from the rising edge of the reference clock (REFCLK). The
REFCLK is the
is divided by four internal ticks: T1, T2, T3, and T4. T1 always occurs at the rising edge of REFCLK (and T3 at the falling
edge), but the spacing of T2 and T4 depends on the PLL clock ratio selected, as Table 13 shows.
Figure 9 is a graphical representation of Table 13.
The UPM machine and GPCM machine outputs change on the internal tick selected by the memory controller configuration.
The AC timing specifications are relative to the internal tick. SDRAM machine outputs change only on the
Freescale Semiconductor
BCLK/SC140 clock
1:4, 1:6, 1:8, 1:10
System Bus Access Timing
1:3
1:5
CLKIN
Core Data Transfers
REFCLK
REFCLK
REFCLK
signal. Memory controller signals, however, trigger on four points within a REFCLK cycle. Each cycle
Figure 9. Internal Tick Spacing for Memory Controller Signals
T1
T1
T1
MSC8113 Tri-Core Digital Signal Processor Data Sheet, Rev. 0
Table 13. Tick Spacing for Memory Controller Signals
T2
T2
T2
2/10 REFCLK
1/4 REFCLK
1/6 REFCLK
T2
T3
T3
T3
Tick Spacing (T1 Occurs at the Rising Edge of REFCLK)
T4
T4
T4
1/2 REFCLK
1/2 REFCLK
1/2 REFCLK
T3
for 1:4, 1:6, 1:8, 1:10
for 1:3
for 1:5
Electrical Characteristics
7/10 REFCLK
3/4 REFCLK
4/6 REFCLK
REFCLK
T4
rising edge.
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