MSC8122MPLOX Freescale Semiconductor / Motorola, MSC8122MPLOX Datasheet
MSC8122MPLOX
Related parts for MSC8122MPLOX
MSC8122MPLOX Summary of contents
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Freescale Semiconductor Data Sheet: Quad Digital Signal Processor • Four StarCore™ SC140 DSP extended cores, each with an SC140 DSP core, 224 Kbyte of internal SRAM M1 memory (1436 Kbyte total), 16 way 16 Kbyte instruction cache (ICache), four-entry write ...
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Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 1.1 ...
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SC140 Extended Core MQBus Boot ROM M2 RAM PLL/Clock JTAG Port System Interface Program Sequencer SC140 Core JTAG Power Management Instruction Cache QBus Notes: 1. The arrows show the data transfer direction. 2. The QBus interface ...
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Pin Assignments 1 Pin Assignments This section includes diagrams of the MSC8122 package ball grid array layouts and pinout allocation tables. 1.1 FC-PBGA Ball Layout Diagrams Top and bottom views of the FC-PBGA package are shown in Figure 3 and ...
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NMI_ V B GND GND GND DD OUT GND TDO GPIO28 HCID1 DD RESET V D TDI EE0 EE1 GND HCID2 DDH TCK TRST TMS HRESET GPIO27 HCID0 E PO RST ...
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Pin Assignments GND GPIO0 GND GPIO6 GPIO5 GPIO3 GPIO7 GPIO1 GPIO2 GPIO30 GPIO8 GND GPIO4 GPIO29 GPIO31 DDH DDH GPIO12 GPIO10 GPIO13 GPIO9 ...
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Signal List By Ball Location Table 1 presents signal list sorted by ball number. - Table 1. MSC8122 Signal Listing by Ball Designator Des. Signal Name GND B5 GND B6 NMI_OUT B7 GND B8 V ...
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Pin Assignments Table 1. MSC8122 Signal Listing by Ball Designator (continued) Des. Signal Name E12 GND E13 V DD E14 GND E15 GND E16 V DD E17 GND E18 GND E19 GPIO9/TDM2TSYN/IRQ7/ETHMDIO E20 GPIO13/TDM2RCLK/IRQ11/ETHMDC E21 GPIO10/TDM2TCLK/IRQ8/ETHRX_DV/ETHCRS_DV/NC E22 GPIO12/TDM2RSYN/IRQ10/ETHRXD1/ETHSYNC F2 PORESET ...
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Table 1. MSC8122 Signal Listing by Ball Designator (continued) Des. Signal Name H21 V DDH H22 A31 J2 HA18 J3 HA26 HA13 J6 GND J7 PSDAMUX/PGPL5 J8 BADDR27 J10 CLKIN J11 BM2/TC2/BNKSEL2 J12 ...
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Pin Assignments Table 1. MSC8122 Signal Listing by Ball Designator (continued) Des. Signal Name M15 V DDH M16 HBRST M17 V DDH M18 V DDH M19 GND M20 V DDH M21 A24 M22 A21 N2 HD26 N3 HD30 N4 HD29 ...
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Table 1. MSC8122 Signal Listing by Ball Designator (continued) Des. Signal Name T6 HWBS7/HDBS7/HWBE7/HDBE7/PWE7/PSDDQM7/PBS7 T7 HWBS5/HDBS5/HWBE5/HDBE5/PWE5/PSDDQM5/PBS5 T8 TSZ0 T9 TSZ2 T10 TBST T11 V DD T12 D16 T13 TT1 T14 D21 T15 D23 T16 IRQ5/DP5/DACK4/EXT_BG3 T17 IRQ4/DP4/DACK3/EXT_DBG3 T18 IRQ1/DP1/DACK1/EXT_BG2 T19 ...
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Pin Assignments Table 1. MSC8122 Signal Listing by Ball Designator (continued) Des. Signal Name W15 V DDH W16 HD33/D33/reserved W17 V DDH W18 HD32/D32/reserved W19 GND W20 GND W21 A7 W22 A6 Y2 HD7 Y3 HD15 Y4 V DDH Y5 ...
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Electrical Characteristics This document contains detailed information on power considerations, DC/AC electrical characteristics, and AC timing specifications. For additional information, see the MSC8122 Reference Manual. 2.1 Maximum Ratings This device contains circuitry protecting against damage due to high static ...
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Electrical Characteristics 2.2 Recommended Operating Conditions Table 3 lists recommended operating conditions. Proper device operation outside of these conditions is not guaranteed. Table 3. Recommended Operating Conditions Rating Core and PLL supply voltage: • Standard — 400 MHz — 500 ...
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DC Electrical Characteristics This section describes the DC electrical characteristics for the MSC8122. The measurements in Table 5 assume the following system conditions: • °C A • — 300/400 MHz 1.1 V nominal ...
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Electrical Characteristics V + 17% DDH DDH V GND V IL GND – 0.3 V GND – 0.7 V Figure 5. Overshoot/Undershoot Voltage for V 2.5 AC Timings The following sections include illustrations and tables ...
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V 2.2 V 1.2 V o.5 V Figure 6. Start-Up Sequence: V 3.3 V 1.2 V o.5 V PORESET/TRST asserted V applied DD Figure 7. Start-Up Sequence: V MSC8122 Quad Digital Signal Processor Data Sheet, Rev. 16 Freescale Semiconductor ...
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Electrical Characteristics In all cases, the power-up sequence must follow the guidelines shown in Figure 1.2 V Figure 8. Power-Up Sequence for V The following rules apply: 1. During time interval A, V DDH The ...
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Characteristic Phase jitter between BCLK and CLKIN CLKIN frequency CLKIN slope 1 CLKIN period jitter CLKIN jitter spectrum PLL input clock (after predivider) PLL output frequency (VCO output) • 300 MHz core • 400 MHz core • 500 MHz core ...
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Electrical Characteristics Table 11 summarizes the reset actions that occur as a result of the different reset sources. Table 11. Reset Actions for Each Reset Source Reset Action/Reset Source Configuration pins sampled (Refer to Section 2.5.4.1 for details). SPLL state ...
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Reset Timing Tables Table 12 and Figure 9 describe the reset timing for a reset configuration write through the direct slave interface (DSI) or through the system bus. Table 12. Timing for a Reset Configuration Write through the DSI ...
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Electrical Characteristics 2.5.5 System Bus Access Timing 2.5.5.1 Core Data Transfers Generally, all MSC8122 bus and system output signals are driven from the rising edge of the reference clock (REFCLK). The REFCLK is the CLKIN signal. Memory controller signals, however, ...
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The UPM machine and GPCM machine outputs change on the internal tick selected by the memory controller configuration. The AC timing specifications are relative to the internal tick. SDRAM machine outputs change only on the No. Characteristic 10 Hold time ...
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Electrical Characteristics No. Characteristic 2 30 Minimum delay from the 50% level of the REFCLK for all signals 31 PSDVAL/TEA/TA max delay from the 50% level of the REFCLK rising edge 32a Address bus max delay from the 50% level ...
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AACK/ARTRY/TA/TEA/DBG/BG/BR Data bus inputs—normal mode Data bus inputs—ECC and parity modes Address bus/TS /TT[0–4]/TC[0–2]/ TBST/TSZ[0–3]/GBL inputs Address bus/TT[0–4]/TC[0–2]/TBST/TSZ[0–3]/GBL outputs Memory controller/ALE outputs AACK/ABB/TS/DBG/BG/BR/DBB/CS outputs MSC8122 Quad Digital Signal Processor Data Sheet, Rev. 16 Freescale Semiconductor REFCLK 11 PSDVAL/ABB/DBB inputs 12 ...
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Electrical Characteristics 2.5.5.2 CLKIN to CLKOUT Skew Table 17 describes the to- CLKOUT- CLKIN No. Characteristic 20 Rise-to-rise skew • 1 • 1 Fall-to-fall skew • 1 ...
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DMA Data Transfers Table 17 describes the DMA signal timing. No. Characteristic 37 DREQ set-up time before the 50% level of the falling edge of REFCLK 38 DREQ hold time after the 50% level of the falling edge of ...
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Electrical Characteristics 2.5.6 DSI Timing The timings in the following sections are based capacitive load. 2.5.6.1 DSI Asynchronous Mode No. Characteristics 1 100 Attributes set-up time before strobe (HWBS[n]) assertion 1 101 Attributes hold time after ...
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Figure 14 shows DSI asynchronous read signals timing. HCS HA[11–29] HCID[0–4] HDST 1 HRW 2 HWBSn 1 HDBSn 2 HRDS HD[0–63] 3 HTA 4 HTA Notes: 1. Used for single-strobe mode access. 2. Used for dual-strobe mode access. 3. HTA ...
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Electrical Characteristics Figure 15 shows DSI asynchronous write signals timing. HCS HA[11–29] HCID[0–4] HDST 1 HRW 2 HRDS 1 HDBSn 2 HWBSn HD[0–63] 3 HTA 4 HTA Notes: 1. Used for single-strobe mode access. 2. Used for dual-strobe mode access. ...
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DSI Synchronous Mode No. Characteristic 1,2 120 HCLKIN cycle time 121 HCLKIN high pulse width 122 HCLKIN low pulse width 123 HA[11–29] inputs set-up time 124 HD[0–63] inputs set-up time 125 HCID[0–4] inputs set-up time 126 All other inputs ...
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Electrical Characteristics 2.5.7 TDM Timing No. Characteristic 300 TDMxRCLK/TDMxTCLK 301 TDMxRCLK/TDMxTCLK high pulse width 302 TDMxRCLK/TDMxTCLK low pulse width 303 TDM receive all input set-up time 304 TDM receive all input hold time 305 TDMxTCLK high to TDMxTDAT/TDMxRCLK output 2,3 ...
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UART Timing No. Characteristics 400 URXD and UTXD inputs high/low duration 401 URXD and UTXD inputs rise/fall time 402 UTXD output rise/fall time UTXD, URXD inputs UTXD output MSC8122 Quad Digital Signal Processor Data Sheet, Rev. 16 Freescale Semiconductor ...
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Timer Timing No. 500 TIMERx frequency 501 TIMERx Input high period 502 TIMERx Output low period 503 TIMERx Propagations delay from its clock input • 1.1 V core • 1.2 V core TIMERx (Input) TIMERx (Output) 2.5.10 Ethernet Timing ...
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MII Mode Timing No. 803 ETHRX_DV, ETHRXD[0–3], ETHRX_ER to ETHRX_CLK rising edge set-up time 804 ETHRX_CLK rising edge to ETHRX_DV, ETHRXD[0–3], ETHRX_ER hold time 805 ETHTX_CLK to ETHTX_EN, ETHTXD[0–3], ETHTX_ER output delay • 1.1 V core • 1.2 V ...
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SMII Mode No. 808 ETHSYNC_IN, ETHRXD to ETHCLOCK rising edge set-up time 809 ETHCLOCK rising edge to ETHSYNC_IN, ETHRXD hold time 810 ETHCLOCK rising edge to ETHSYNC, ETHTXD output delay • 1.1 V core. • 1.2 V core. Notes: ...
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REFCLK 603 GPIO (Output) GPIO (Input) 2.5.12 EE Signals Number Characteristics 65 EE0 (input) 66 EE1 (output) Notes: 1. The core clock is the SC140 core clock. The ratio between the core clock and CLKOUT is configured during power-on-reset. 2. ...
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No. 704 Boundary scan input data set-up time 705 Boundary scan input data hold time 706 TCK low to output data valid 707 TCK low to output high impedance 708 TMS, TDI data set-up time 709 TMS, TDI data hold ...
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TCK V (Input) IL TDI TMS (Input) TDO (Output) TDO (Output) Figure 31. Test Access Port Timing Diagram TCK (Input) TRST (Input) 712 3 Hardware Design Considerations The following sections discuss areas to consider when the MSC8122 device is designed ...
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Hardware Design Considerations • Never allow V to exceed V DD supply to prevent reverse current flow by adding a minimum 10 Ω resistor to GND to limit the • Design the V DDH current. Such a design yields an ...
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Figure 34. For optimal noise filtering, place the circuit as close as possible followed by the 10-µF capacitor, the 10-nH inductor, and finally the 10-Ω resistor to V CCSYN kept short and direct. Provide an extremely low ...
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Hardware Design Considerations Note: The MSC8122 does not support DLL-enabled mode. For the following two clock schemes, ensure that the DLL is disabled (that is, the DLLDIS bit in the Hard Reset Configuration Word is set). • system ...
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Thermal Considerations An estimation of the chip-junction temperature where T = ambient temperature near the package (° θ = junction-to-ambient thermal resistance (°C/ power dissipation in the package (W) D ...
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Package Information 5 Package Information Figure 35. MSC8122 Mechanical Information, 431-pin FC-PBGA Package 6 Product Documentation • MSC8122 Technical Data Sheet (MSC8122). Details the signals, AC/DC characteristics, clock signal characteristics, package and pinout, and electrical design considerations of the MSC8122 ...
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Revision History Table 31 provides a revision history for this data sheet. Revision Date 0 May 2004 • Initial release. 1 Jun. 2004 • Updated timing number 32b. • Updated DSI timing specifications. 2 Sep 2004 • New orderable ...
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Revision History MSC8122 Quad Digital Signal Processor Data Sheet, Rev Freescale Semiconductor ...
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MSC8122 Quad Digital Signal Processor Data Sheet, Rev. 16 Freescale Semiconductor Revision History 47 ...
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