MSC8126 Freescale Semiconductor / Motorola, MSC8126 Datasheet
MSC8126
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MSC8126 Summary of contents
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... FIFOs per channel, FIFO generated watermarks and hungry requests, priority-based time-multiplexing between channels using 16 internal priority © Freescale Semiconductor, Inc., 2004, 2007. All rights reserved. Document Number: MSC8126 MSC8126 FC PBGA–431 20 mm × levels or round-robin time-multiplexing between channels, flexible channel configuration with connection to local bus or system bus, and flyby transfer support that bypasses the FIFO ...
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... Package Information .45 6 Product Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 7 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 List of Figures Figure 1. MSC8126 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . 3 Figure 2. StarCore SC140 DSP Extended Core Block Diagram . . 3 Figure 3. MSC8126 Package, Top View . . . . . . . . . . . . . . . . . . . . 5 Figure 4. MSC8126 Package, Bottom View . . . . . . . . . . . . . . . . . . 6 Figure 5. Overshoot/Undershoot Voltage for V Figure 6. Start-Up Sequence: V and V DD DDH Figure 7 ...
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... The QBus interface includes a bus switch, write buffer, fetch unit, and a control unit that defines four QBus banks. In addition, the QBC handles internal memory contentions. Figure 2. StarCore SC140 DSP Extended Core Block Diagram MSC8126 Quad Digital Signal Processor Data Sheet, Rev. 13 Freescale Semiconductor SC140 ...
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... Pin Assignments 1 Pin Assignments This section includes diagrams of the MSC8126 package ball grid array layouts and pinout allocation tables. 1.1 FC-PBGA Ball Layout Diagrams Top and bottom views of the FC-PBGA package are shown in Figure 3 and Figure 4 with their ball location index numbers. ...
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... HD7 HD15 HD9 HD60 DDH HD14 HD12 HD10 HD63 HD59 DD AB GND HD13 HD11 HD8 HD62 HD61 MSC8126 Quad Digital Signal Processor Data Sheet, Rev. 13 Freescale Semiconductor Top View GND GND GND GND ...
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... DDH HD34 HD37 GND DDH HD35 HD38 HD42 HD36 HD39 HD41 HD44 DD MSC8126 Quad Digital Signal Processor Data Sheet, Rev Bottom View GND GND GND GND GND GND DD DD ...
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... C10 GND C11 V DD C12 GND C13 V DD C14 GND C15 GND C16 GPIO30/TIMER2/TMCLK/SDA C17 GPIO2/TIMER1/CHIP_ID2/IRQ6 MSC8126 Quad Digital Signal Processor Data Sheet, Rev. 13 Freescale Semiconductor Des. Signal Name C18 GPIO1/TIMER0/CHIP_ID1/IRQ5/ETHTXD1 C19 GPIO7/TDM3RCLK/IRQ5/ETHTXD3 C20 GPIO3/TDM3TSYN/IRQ1/ETHTXD2 C21 GPIO5/TDM3TDAT/IRQ3/ETHRXD3 C22 GPIO6/TDM3RSYN/IRQ4/ETHRXD2 D2 TDI D3 EE0 ...
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... GPIO16/TDM1TCLK/DONE1/DRACK1 F20 GPIO11/TDM2TDAT/IRQ9/ETHRX_ER/ETHTXD F21 GPIO14/TDM2RDAT/IRQ12/ETHRXD0/NC F22 GPIO19/TDM1RCLK/DACK2 G2 HA24 G3 HA27 G4 HA25 G5 HA23 H21 V DDH H22 A31 J2 HA18 MSC8126 Quad Digital Signal Processor Data Sheet, Rev Des. Signal Name G6 HA17 G7 PWE0/PSDDQM0/PBS0 G10 IRQ3/BADDR31 G11 BM0/TC0/BNKSEL0 G12 ABB/IRQ4 G13 V DD ...
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... GND K14 CLKOUT M15 V DDH M16 HBRST M17 V DDH M18 V DDH M19 GND M20 V DDH MSC8126 Quad Digital Signal Processor Data Sheet, Rev. 13 Freescale Semiconductor Des. Signal Name K18 CS2 K19 GND K20 A26 K21 A29 K22 A28 L2 HA12 L3 HA14 L4 HA11 ...
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... GND SYN T6 HWBS7/HDBS7/HWBE7/HDBE7/PWE7/PSDDQM7/PBS7 T7 HWBS5/HDBS5/HWBE5/HDBE5/PWE5/PSDDQM5/PBS5 T8 TSZ0 T9 TSZ2 T10 TBST T11 V DD T12 D16 T13 TT1 T14 D21 MSC8126 Quad Digital Signal Processor Data Sheet, Rev Des. Signal Name P18 PSDVAL P19 DP0/DREQ1/EXT_BR2 P20 V DDH P21 GND P22 A19 R2 HD18 R3 V DDH R4 ...
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... W18 HD32/D32/reserved W19 GND W20 GND W21 A7 W22 A6 Y2 HD7 Y3 HD15 Y4 V DDH Y5 HD9 MSC8126 Quad Digital Signal Processor Data Sheet, Rev. 13 Freescale Semiconductor Des. Signal Name V9 D7 V10 D10 V11 D12 V12 D13 V13 D18 V14 D20 V15 GND V16 ...
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... Y21 A4 Y22 A5 AA2 V DD AA3 HD14 AA4 HD12 AA5 HD10 AA6 HD63/D63 AA7 HD59/D59/ETHMDIO AA8 GND MSC8126 Quad Digital Signal Processor Data Sheet, Rev Des. Signal Name AA21 A2 AA22 A3 AB2 GND AB3 HD13 AB4 HD11 AB5 HD8 AB6 HD62/D62 AB7 ...
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... Therefore, a “maximum” value for a specification never occurs in the same device with a “minimum” value for another specification; adding a maximum to a minimum represents a condition that can never exist. Table 2 describes the maximum electrical ratings for the MSC8126. Rating Core and PLL supply voltage ...
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... Reduced (300 and 400 MHz) I/O supply voltage Input voltage Operating temperature range: • Standard • Extended 2.3 Thermal Characteristics Table 4 describes thermal characteristics of the MSC8126 for the FC-PBGA packages. Table 4. Thermal Characteristics for the MSC8126 Characteristic 1, 2 Junction-to-ambient 1, 3 Junction-to-ambient, four-layer board 4 ...
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... DC Electrical Characteristics This section describes the DC electrical characteristics for the MSC8126. The measurements in Table 5 assume the following system conditions: • °C A • — 400 MHz = 1.14–1.26 V — 500 MHz = 1.16–1.24 V • = 3.3 V ± DDH DC • GND DC Note: The leakage current is measured for nominal ...
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... See Section 3.1 for start-up sequencing recommendations and Section 3.2 for power supply design recommendations. The following figures show acceptable start-up sequence examples. Figure 6 shows a sequence in which raised together. Figure 7 shows a sequence in which MSC8126 Quad Digital Signal Processor Data Sheet, Rev DDH Must not exceed 10% of clock period Table 6 ...
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... V 2.2 V 1.2 V o.5 V Figure 6. Start-Up Sequence: V 3.3 V 1.2 V o.5 V PORESET/TRST asserted V applied DD Figure 7. Start-Up Sequence: V MSC8126 Quad Digital Signal Processor Data Sheet, Rev. 13 Freescale Semiconductor V = Nominal Value DDH V = Nominal Value DD 1 PORESET/TRST Deasserted CLKIN Starts Toggling PORESET/TRST Asserted V /V Applied DD DDH and V DD ...
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... Characteristics CLKIN frequency BCLK frequency Reference clock (REFCLK) frequency Output clock (CLKOUT) frequency SC140 core clock frequency Note: The rise and fall time of external clocks should maximum MSC8126 Quad Digital Signal Processor Data Sheet, Rev DDH CCSYN ...
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... Host reset command through JTAG All MSC8126 reset sources are fed into the reset controller, which takes different actions depending on the source of the reset. The reset status register indicates the most recent sources to cause a reset. Table 10 describes the reset sources. ...
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... Through the direct slave interface (DSI) • Through the system bus. When the reset configuration is written through the system bus, the MSC8126 acts as a configuration master or a configuration slave. If configuration slave is selected, but no special configuration word is written, a default configuration word is applied. ...
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... Input PORESET Internal HRESET Output (I/O) SRESET Output (I/O) Figure 9. Timing Diagram for a Reset Configuration Write MSC8126 Quad Digital Signal Processor Data Sheet, Rev. 13 Freescale Semiconductor , CNFGS, DSISYNC, DSI64, RSTCONF , RSTCONF, CNFGS, DSISYNC, DSI64 CHIP_ID[0–3], BM[0–2], SWTE, MODCK[1–2] pins are sampled ...
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... System Bus Access Timing 2.5.5.1 Core Data Transfers Generally, all MSC8126 bus and system output signals are driven from the rising edge of the reference clock (REFCLK). The REFCLK is the CLKIN signal. Memory controller signals, however, trigger on four points within a REFCLK cycle. Each cycle is divided by four internal ticks: T1, T2, T3, and T4 ...
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... Timings specifications 13 and 14 in non-pipeline mode are more restrictive than MSC8102 timings. 2. Values are measured from the 50% TTL transition level relative to the 50% level of the REFCLK rising edge. 3. Guaranteed by design MSC8126 Quad Digital Signal Processor Data Sheet, Rev. 13 Freescale Semiconductor Table 14. AC Timing for SIU Inputs Value for Bus Speed in MHz 133 ...
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... The maximum bus frequency depends on the mode 60x-compatible mode connected to another MSC8126 device, the frequency is determined by adding the input and output longest timing values, which results in the total delay for 20 pF output capacitance. You must also account for other influences that can affect timing, such as on-board clock skews, on-board noise delays, and so on. ...
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... Data bus inputs—ECC and parity modes Address bus/TS /TT[0–4]/TC[0–2]/ TBST/TSZ[0–3]/GBL inputs Address bus/TT[0–4]/TC[0–2]/TBST/TSZ[0–3]/GBL outputs Memory controller/ALE outputs AACK/ABB/TS/DBG/BG/BR/DBB/CS outputs MSC8126 Quad Digital Signal Processor Data Sheet, Rev. 13 Freescale Semiconductor REFCLK 11 PSDVAL/ABB/DBB inputs 12 ...
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... CLKOUT synchronization mode, use the skew values listed in Table 16 to adjust the rise-to-fall timing values specified for synchronization. Figure 12 shows the relationship between the CLKIN MSC8126 Quad Digital Signal Processor Data Sheet, Rev skew timing. Table 16. CLKOUT Skew CLKIN ...
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... DACK/DRACK/DONE delay after the 50% level of the REFCLK rising edge signal is synchronized with The DREQ according to the timings in Table 17. Figure 13 shows synchronous peripheral interaction. DACK/DONE/DRACK MSC8126 Quad Digital Signal Processor Data Sheet, Rev. 13 Freescale Semiconductor Table 17. DMA Signals . To achieve fast response, a synchronized peripheral should assert REFCLK ...
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... Attributes refers to the following signals: HCS, HA[11–29], HCID[0–4], HDST, HRW, HRDS, and HWBSn. 2. This specification is tested in dual-strobe mode. Timing in single-strobe mode is guaranteed by design. 3. All values listed in this table are tested or guaranteed by design. MSC8126 Quad Digital Signal Processor Data Sheet, Rev Table 18. DSI Asynchronous Mode Timing 2 Min Max 1 ...
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... HTA released at logic 0 (DCR[HTAAD end of access; used with pull-down implementation. 4. HTA released at logic 1 (DCR[HTAAD end of access; used with pull-up implementation. Figure 14. Asynchronous Single- and Dual-Strobe Modes Read Timing Diagram MSC8126 Quad Digital Signal Processor Data Sheet, Rev. 13 Freescale Semiconductor 100 101 112 102 ...
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... HRDS 1 HDBSn 2 HWBSn HD[0–63] Notes: 1. Used for single-strobe mode access. 2. Used for dual-strobe mode access. Figure 16. Asynchronous Broadcast Write Timing Diagram MSC8126 Quad Digital Signal Processor Data Sheet, Rev 100 112 201 106 108 100 112 201 202 101 102 ...
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... HCID[0–4] input signals All other input signals HD[0–63] output signals HTA output signal Figure 17. DSI Synchronous Mode Signals Timing Diagram MSC8126 Quad Digital Signal Processor Data Sheet, Rev. 13 Freescale Semiconductor Table 19. DSI Inputs—Synchronous Mode Expression (0.5 ± 0.1) × HTC (0.5 ± 0.1) × HTC ...
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... Values are based maximum frequency of 62.5 MHz. The TDM interface supports any frequency below 62.5 MHz. 2. Values are based capacitive load. 3. When configured as an output, TDMxRCLK acts as a second data link. See the MSC8126 Reference Manual for details. 4. CLKOUT synchronization is not supported for cores operating at above 400 MHz. 5. ...
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... URXD and UTXD inputs high/low duration 401 URXD and UTXD inputs rise/fall time 402 UTXD output rise/fall time UTXD, URXD inputs UTXD output MSC8126 Quad Digital Signal Processor Data Sheet, Rev. 13 Freescale Semiconductor Table 22. UART Timing Expression 16 × T 401 401 400 Figure 20 ...
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... No. 801 ETHMDIO to ETHMDC rising edge set-up time 802 ETHMDC rising edge to ETHMDIO hold time ETHMDC ETHMDIO Figure 23. MDIO Timing Relationship to MDC MSC8126 Quad Digital Signal Processor Data Sheet, Rev Table 23. Timer Timing Characteristics 500 501 502 503 Figure 22. Timer Timing ...
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... ETHREF_CLK rising edge to ETHTXD[0–1], ETHTX_EN output delay. ETHREF_CLK ETHCRS_DV ETHRXD[0–1] ETHRX_ER ETHTX_EN ETHTXD[0–1] MSC8126 Quad Digital Signal Processor Data Sheet, Rev. 13 Freescale Semiconductor Table 25. MII Mode Signal Timing Characteristics 803 Valid 805 Valid Figure 24. MII Mode Signal Timing Table 26 ...
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... REFCLK edge to high impedance on GPIO out 604 GPIO in valid to REFCLK edge (GPIO in set-up time) 605 REFCLK edge to GPIO in not valid (GPIO in hold time) MSC8126 Quad Digital Signal Processor Data Sheet, Rev Table 27. SMII Mode Signal Timing Characteristics 808 809 ...
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... TCK cycle time 702 TCK clock pulse width measured at V • High • Low 703 TCK rise and fall times MSC8126 Quad Digital Signal Processor Data Sheet, Rev. 13 Freescale Semiconductor High Impedance 604 605 Valid Figure 27. GPIO Timing Table 29. EE Pin Timing Type ...
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... Figure 29. Test Clock Input Timing Diagram TCK V (Input) IL Data Inputs Data Outputs Data Outputs Figure 30. Boundary Scan (JTAG) Timing Diagram MSC8126 Quad Digital Signal Processor Data Sheet, Rev Table 30. JTAG Timing (continued) Characteristics 701 703 704 ...
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... TDO (Output) TDO (Output) Figure 31. Test Access Port Timing Diagram TCK (Input) TRST (Input) 712 MSC8126 Quad Digital Signal Processor Data Sheet, Rev. 13 Freescale Semiconductor 708 Input Data Valid 710 Output Data Valid 711 713 Figure 32. TRST Timing Diagram V IH ...
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... When used as a drop-in replacement in MSC8102 applications or when implementing a new design, use the guidelines described in Migrating Designs from the MSC8102 to the MSC8122 (AN2716) and the MSC8126 Design Checklist (AN3374 for optimal system performance. MSC8122 and MSC8126 Power Circuit Design Recommendations and Examples (AN2937) provides detailed design information ...
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... For best results, place this capacitor on the backside of the PCB aligned with the depopulated void on the MSC8126 located in the square defined by positions, L11, L12, L13, M11, M12, M13, N11, N12, and N13. ...
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... SDRAM) making sure that the delay path the CLKIN between the clock buffer to the MSC8126 and the SDRAM is equal (that is, has a skew less than 100 ps). — Valid clock modes in this scheme are 15, 19, 21, 23, 28, 29, 30, and 31. ...
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... For example, for 166 MHz operation, you may have to use 183 or 200 MHz SDRAM. Always perform a detailed timing analysis using the MSC8126 bus timing values and the manufacturer specifications for the SDRAM to ensure correct operation within your system design. The output delay listed in SDRAM specifications is usually given for a load ...
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... I/O The power dissipation values for the MSC8126 are listed in Table 2-3. The ambient temperature for the device is the air temperature in the immediate vicinity that would cool the device. The junction-to-ambient thermal resistances are JEDEC standard values that provide a quick and easy estimation of thermal performance. There are two values in common usage: the value determined on a single layer board and the value obtained on a board with two planes ...
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... MSC8126 Reference Manual (MSC8126RM). Includes functional descriptions of the extended cores and all the internal subsystems including configuration and programming information. • Application Notes. Cover various programming topics related to the StarCore DSP core and the MSC8126 device. • SC140 DSP Core Reference Manual. Covers the SC3400 core architecture, control registers, clock registers, program control, and instruction set ...
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... Added power-sequence guidelines to Sections 2.5.2. • Added CLKIN jitter characteristic specifications to • Added additional guidelines to prevent reverse current to Section 3.1. • Added connectivity guidelines for DSI in sliding windows mode to Section 3.3. MSC8126 Quad Digital Signal Processor Data Sheet, Rev Table 31. Document Revision History Description 2 C timing changed to GPIO timing ...
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... MSC8126 Quad Digital Signal Processor Data Sheet, Rev. 13 Freescale Semiconductor Revision History 47 ...
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... Denver, Colorado 80217 +1-800 441-2447 or +1-303-675-2140 Fax: +1-303-675-2150 LDCForFreescaleSemiconductor @hibbertgroup.com Document Number: MSC8126 Rev. 13 12/2007 Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document ...