CS3810 Amphion Semiconductor Ltd., CS3810 Datasheet

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... Table 1: CS3810 32 QAM Demodulator Interface Signal Descriptions Name I/O RESTART Input INPUT DATA ZIFMT Input ZA Input ZB Input AGC SETTING AGCREF Input BLL SETTINGS VCORNG Input HBWBLL Input FFKBLL Input LFFKBLL Input LCKTHBLL Input LCKWINBLL Input Width 1 Synchronous reset signal, active HIGH. The BLL restart the acquisition process after it is activated ...

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... CS3810 32 QAM Demodulator Table 1: CS3810 32 QAM Demodulator Interface Signal Descriptions Name I/O CLL SETTINGS INIPCLL Input AFCCLL Input NAFCCLL Input PILBWCLL Input DDLBWCLL Input MUCMAEQ Input MUDDEQ Input OUTPUT DATA RXSYNC Output RXDATA Output 4 Width 1 CLL initial period selection, in terms of 32-QAM symbols, static program- ...

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... Table 1: CS3810 32 QAM Demodulator Interface Signal Descriptions Name I/O ERROR CORRECTION STATISTICS TCMERR Output RSERR_U Output RSERR_L Output AGC CONTROL AGCP Output VCO CONTROL VCOV Output VCSTRB Output ERROR CORRECTION CONTROL RSERRPRD Input UPTCM Input BYPASS Input LOCK STATUS AGCOK Output LCKBLL ...

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... CS3810 32 QAM Demodulator Table 1: CS3810 32 QAM Demodulator Interface Signal Descriptions Name I/O TEST DATA BLLSTRB Output BLLIQ Output BLLQI Output MAPI Input MAPQ Input MapStrb Input MapTest Input MICROPROCESSOR INTERFACE DATA Tri-state ADDR Input ALE Input CSB Input WRB Input OEB Input ...

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The input to the demodulator may be fed directly from converter. It samples the received spectrum at double the symbol rate. AGC An AGC loop is implemented with an external gain control element in order to achieve ...

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... CS3810 32 QAM Demodulator The programming signals are assumed to be static, i.e., they do not change during normal operation process. The microprocessor interface signals have been described in the CLK ZA ZB Figure 4: Input Data Timing CLK ZSTRB AGCP AGCOK Figure 5: AGC Control Timing CLK BLLSTRB ...

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Figure 7 demonstrates the over all error correction performance of the Concatenated correction system employed by the decoder (under AWGN conditions). 10 1.00E+00 1.00E-01 1.00E-02 1.00E-03 1.00E-04 1.00E-05 1.00E-06 1.00E-07 1.00E-08 Figure 7: Error Correction Performance The demodulator. acquisition performance ...

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... Note that the metrics are provided for demodulation (Table 3) and channel decoding (Table 4) separately. Table 3: CS3810 FEC Decoder Programmable Logic Core - Altera DEVICE SILICON VENDOR APEX20KC-7 Altera Table 4: CS3810 Symbol & Timing Recovery Programmable Logic Core - Altera DEVICE SILICON VENDOR APEX20KC-7 Altera 10 ...

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Typical ASIC or FPGA Design Flow (Conceptual) System-Level "C" Code simulation Hardware RTL Development RTL Simulation Logic Synthesis Gate-level analysis (timing & functional) Physical Design Figure 8: Design Data Formats Supplied by Amphion Data Formats Supplied by AMPHION Bit Accurate ...

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... CS3810 32 QAM Demodulator ABOUT AMPHION Amphion (formerly Integrated Silicon Systems) is the leading supplier of speech coding, video/ image processing and channel coding application specific silicon cores for system-on-a-chip (SoC) solutions in the broadband, wireless, and mulitmedia markets Web: www.amphion.com Email: info@amphion.com SALES AGENTS ...