A43E06161 AMIC Technology, Corp., A43E06161 Datasheet - Page 33

• Manufacturer Part Number: A43E06161
• Description: 512K x 16-Bit x 2 Banks Synchronous DRAM
• Manufacturer: AMIC Technology, Corp.

Read Interrupted by Precharge Command & Read Burst Stop Cycle (@Burst Length = Full Page)
PRELIMINARY
CLOCK
A10/AP
ADDR
(CL=2)
(CL=3)
RAS
CAS
CKE
DQM
CS
BA
DQ
DQ
WE
0
* Note : 1. At full page mode, burst is wrap-around at the end of burst. So auto precharge is impossible.
Row Active
(A-Bank)
RAa
RAa
1
2. About the valid DQ’s after burst stop, it is same as the case of
3. Burst stop is valid at every burst length.
(July, 2005, Version 0.1)
Both cases are illustrated above timing diagram. See the label 1,2 on them.
But at burst write, burst stop and RAS interrupt should be compared carefully.
Refer the timing diagram of “Full page write burst stop cycle”.
2
3
(A-Bank)
* Note 1
Read
CAa
4
5
QAa0
6
QAa0
QAa1 QAa2
7
QAa1
8
* Note 2
Burst Stop
QAa3
QAa2
9
32
High
QAa4
QAa3
10
1
* Note 1
(A-Bank)
QAa4
Read
CAb
11
2
RAS interrupt.
12
QAb0 QAb1 QAb2 QAb3
13
QAb0
14
QAb1 QAb2 QAb3
AMIC Technology, Corp.
15
16
Precharge
(A-Bank)
QAb4 QAb5
17
A43E06161
QAb4 QAb5
: Don't care
18
1
19
2