STE2004 STMicroelectronics, STE2004 Datasheet
STE2004
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STE2004 Summary of contents
Page 1
... Display Supply Voltage range from 4.5 to 14.5V Backward Compatibility with STE2001/2 2 DESCRIPTION The STE2004 is a low power CMOS LCD control- ler driver. Designed to drive a 65 rows by 102 col- umns graphic display, it provides all necessary functions in a single chip, including on-chip LCD supply and bias voltages generators, resulting in a minimum of externals components and in a very low power consumption ...
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... STE2004 Table 2. Pin Description N° Pad Type R0 to R64 1-6 O 109-141 C0 to C101 6-107 O V 192-203 GND SS V 156-163 Supply DD1 V 164-171 Supply DD2 V 205-209 Supply LCD V 204 Supply LCDSENSE V 145 Supply SENSE_SLAVE V 190-177- O SSAUX 147 V 142 O DD1AUX SEL1,2,3 152 153 154 ...
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... CANNOT BE LEFT FLOATING I Master/Slave Configuration Bit:- CANNOT BE LEFT FLOATING M/S PIN OSC_OUT FR_OUT High ENABLED Enabled Low ENABLED Enabled Function Configuration Internal Oscillator Enabled Internal Oscillator Disabled Internal Oscillator Disabled FR_IN Charge Pump Disabled AuxVsense Disabled Enabled Charge Pump in Slave Mode or Ext Power STE2004 3/66 ...
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... STE2004 Figure 2. Chip Mechanical Drawing COL 50 COL 51 COL 101 ROW 32 ROW 37 4/66 MARK_1 ROW 5 ROW 0 COL 0 MARK_3 STE2004 (0, MARK_4 MARK_2 ROW28 ROW31 FR_OUT OSC_OUT VLCD VLCDSENSE VSS TEST_MODE VSSAUX SCLK - SCL SDOUT SDIN - SDAIN SDAOUT VSSAUX ...
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... ....... (t) = C1(t) - R0( (t) = C1(t) - R1(t) 2 ....... ..... 64 FRAME LCD LCD LCD LCD ..... 64 FRAME D00IN1154 STE2004 V ( (t) 2 5/66 ...
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... STE2004 and the internal Charge Pump of both device. If M/S is connected to VDD1, the driver is configured to work in Master Mode. When STE2004 is in Master Mode the Vsense_Slave Pin is disabled and is possible to control the VLCD value using Vop Bits. The Master Time Generator outputs on FR_OUT and on OSC_OUT the relevant timing references ...
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... Figure 6. Bias level Generator thus providing an 1/(n+4) ratio, with n calculated from: For and an 1/9 ratio is set. For and an 1/8 ratio is set. The STE2004 provides three bits (BS0, BS1, BS2) for programming the desired Bias Ratio as shown below: OSCOUT FROUT FRIN ...
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... STE2004 Table 3. BS2 The following table Bias Level for and are provided: Table 4. Symbol 3.6 LCD Voltage Generation The LCD Voltage at reference temperature (To = 27°C) can be set using the VOP register content according to ...
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... As the viscosity, and therefore the contrast, of the LCD are subject to change with temperature, there's the need to vary the LCD Voltage with temperature. STE2004 provides the possibility to change the VLCD in a linear fashion against temperature with eight different Temperature Coefficient selectable through T2, T1 and T0 bits ...
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... STE2004 3.8 Display Data RAM The STE2004, provides an 102X65 bits Static RAM to store Display data. This is organized into 9 (Bank0 to Bank8) banks with 102 Bytes. One of these Banks can be used for Icons. RAM access is accomplished in either one of the Bus Interfaces provided (see below). Allowed addresses are X0 to X101 (Horizontal) and (Vertical) ...
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... Figure 11. Automatic data RAM writing sequence with V=1 and Data RAM Mirrored Format (MX=1) 101 BANK 0 BANK 1 BANK 2 BANK 3 BANK 4 BANK 5 BANK 6 BANK 7 BANK Carriage=101; Y-Carriage = 100 99 98 100 99 98 STE2004 98 99 100 101 LR0049 98 99 100 101 LR0050 LR0051 LR0052 11/ ...
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... STE2004 Figure 12. Automatic data RAM writing sequence with X-Y Carriage Return (V=0; MX= BANK 0 BANK 1 BANK 2 Y CARR BANK 7 BANK 8 Figure 13. Automatic data RAM writing sequence with X-Y Carriage Return (V=1; MX= BANK 0 BANK 1 BANK 2 Y CARR BANK 7 BANK 8 Figure 14. Automatic data RAM writing sequence with X-Y Carriage Return (V=0; MX=1) ...
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... BANK 0 BANK 1 BANK 2 BANK 3 BANK 4 LSB BANK 5 BANK 6 BANK 7 BANK 8 Figure 17. Data RAM Byte organization with LSB BANK 0 BANK 1 BANK 2 BANK 3 BANK 4 MSB BANK 5 BANK 6 BANK 7 BANK STE2004 98 99 100 101 LR0057 98 99 100 101 LR0058 13/66 ...
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... STE2004 Figure 18. Memory Rows vs. Row Drivers Mapping ICON_MODE=1 and MUX Address Y-CARRIAGE ...
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... 100 101 STE2004 ROW Output Normal Reverse direction direction R0 R64 R1 R63 R2 R62 R3 R61 R4 R60 R5 R59 R6 R58 R7 R57 R8 R56 R9 R55 R10 R54 R11 R53 R12 R52 R13 ...
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... STE2004 Figure 20. Memory Rows vs. Row Drivers Mapping ICON_MODE=1, Y-Carriage<=6 and MUX Address ...
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... 100 101 STE2004 ROW Output Normal Reverse direction direction R0 R56 R1 R55 R2 R54 R3 R53 R4 R52 R5 R51 R6 R50 R7 R49 R8 R48 R9 R47 R10 R46 R11 R45 R12 R44 R13 ...
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... STE2004 Figure 22. Memory Rows vs. Row Drivers Mapping ICON_MODE=0, Y-Carriage=7, Scrolling Pointer>07h and MUX Address ...
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... 100 101 STE2004 ROW Output Normal Reverse direction direction R0 R55 R1 R54 R2 R53 R3 R52 R4 R51 R5 R50 R6 R49 R7 R48 R8 R47 R9 R46 R10 R45 R11 R44 R12 R43 R13 ...
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... STE2004 Figure 24. Memory Rows vs. Row Drivers Mapping ICON_MODE=1, Y-Carriage=8, Scrolling Pointer<10h and MUX Address ...
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... 100 101 STE2004 ROW Output Reverse direction R0 R56 R1 R55 R2 R54 R3 R53 R4 R52 R5 R51 R6 R50 R7 R49 R8 R48 R9 R47 R10 R46 R11 R45 R12 R44 R13 R43 R14 ...
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... STE2004 Figure 26. Memory Rows vs. Row Drivers Mapping ICON_MODE=1, Y-Carriage<=4 and MUX33 D Y Address ...
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... 100 101 STE2004 ROW Output Normal Reverse direction direction R0 R48 R1 R47 R2 R46 R3 R45 R4 R44 R5 R43 R6 R42 R7 R41 R8 R40 R9 R39 R10 R38 R11 R37 R12 R36 R13 ...
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... R61 R62 R63 R64 ICON MUX 49 COLUMN DRIVERS R32 R33 R34 R35 R36 R37 R38 R39 R40 R41 R42 R43 R44 STE2004 R45 R46 R47 R48 R49 R50 R51 R52 R53 R54 R55 R56 R57 R58 R59 R60 R61 R62 R63 ...
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... R45 R46 R47 R48 R49 R50 R51 R52 R53 R54 R55 R56 R57 R58 R59 R60 R61 R62 R63 R64 STE2004 ROW DRIVERS R10 R11 R12 R13 R14 R15 R16 R17 ...
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... BUS INTERFACES To provide the widest flexibility and ease of use the STE2004 features Six different methods for interfacing the host Controller. To select the desired interface the SEL1, SEL2 and SEL3 pads need to be connected to a logic LOW (connect to GND logic HIGH (connect to VDD). All the I/O pins of the unused inter- faces must be connected to GND ...
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... SDA line can be significant, a potential divider is generated by the bus pull-up resistor and the Indium Tin Oxide (ITO) track resistance possible that during the acknowledge cycle the STE2004 will not be able to create a valid logic 0 level. By splitting the SDA input from the output the device could be used in a mode that ignores the acknowledge bit ...
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... STE2004 4.1.2 Writing Mode. If the R/W bit is set to logic 0 the STE2004 is set receiver. After the slaves acknowledge one or more command word follows to define the status of the device. A command word is composed by three bytes. The first is a control byte which defines the Co and D/C values, the second and third are data bytes. The Co bit is the command MSB and defines if after this com- mand will follow two data bytes and an other command word or if will follow a stream of data ( Com- mand word Stream of data) ...
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... DB5 LSB LR0071 DB4 DB3 DB2 DB1 DB0 DB7 Don't Don't Don't Don't Don't Care Care Care Care Care High-Z DB4 DB3 DB2 DB1 DB0 ID Number High-Z DB4 DB3 DB2 DB1 DB0 STATUS BYTE DATA Read LR00076 STE2004 DB6 DB5 LR0072 29/66 ...
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... It consists of three lines: one/two for data signals (SDIN,SDOUT), one for clock signals (SCLK) and one for peripheral enable (CS). If the R/W bit is set to logic 0 the STE2004 is set receiver. One or more command word follows to define the status of the device. A command word is composed by two bytes. The first is a control byte which defines Co, D/C, R/W H[1;0] and HE values, the second is a data byte (fig 39) ...
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... DATA Byte = Command DATA Byte = DDRAM Data if D/C=1 LR0002 Don't Don't Don't Don't Don't Don't Care Care Care Care Care Care High-Z DB5 DB4 DB3 DB2 DB1 DB0 ID-Number High-Z DB5 DB4 DB3 DB2 DB1 DB0 STATUS BYTE DATA Read LR0077 STE2004 if D/C=0 31/66 ...
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... The serial interface is active only if the CS line is set to a logic 0. When CS line is high the serial peripheral power consumption is zero. While CS pin is high the serial interface is kept in reset. The STE2004 is always a slave on the bus and receive the communication clock on the SCLK pin from the master. ...
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... DB3 DB2 DB1 DB0 D/C Don't Don't Don't Don't Don't Don't Care Care Care Care Care Care High-Z DB5 DB4 DB3 DB2 DB1 DB0 ID-Number High-Z DB5 DB4 DB3 DB2 DB1 DB0 STATUS BYTE DATA Read 1 LR0080 STE2004 DB7 DB6 LR0074 LR0075 33/66 ...
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... STE2004 4.3 Parallel Interface The STE2004 selectable parallel Interfaces are 68000-series and 8080-series. They are both an 8-bits bi- directional link between the display driver and the application supervisor. Throughout both parallel interfaces can be read the I 4.3.1 68000-series parallel interface low after the positive edge of RES, the 68000 parallel interface is ready to receive or transmit data. ...
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... Data are output on D0-D7 bus on RD rising edge. Data Bus is set in high impedance mode when RD is set to logic 1. Accordingly to R bit value I2C Address or Status Byte is output on D0-D7 bus. Figure 49. 8080-series parallel bus protocol - one byte transmission CS D/C R Always the same data is output on D0- LR0082 LR0046 LR0083 STE2004 35/66 ...
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... STE2004 Figure 50. 8080-series parallel bus protocol - several bytes transmission CS D Figure 51. 8080-series Parallel interface protocol in Reading Mode Figure 52. 8080-series Parallel interface protocol in Reading Mode (Several Bytes Note 1) Data Bus is configured in high impedence mode after every RD rising edge ...
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... Board Procedure" only under the following conditions bit = 0 - Frame Rate (FR[1:0]=”75Hz”) - Power Down ( Dual Partial Display Disabled (PE= Y-CARRIAGE=8 - X-CARRIAGE=101 (display off). Bias generator and and then is possible to disconnect V SS STE2004 generator LCD ). The internal LCDOUT 37/66 ...
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... C interface). 5.5 Scrolling Function The STE2004 can scroll the graphics display in units of raster-rows. The scrolling function is achieved changing the correspondence between the rows of the logical memory map and the output row drivers. The scroll function doesn't affect the data ram content only related to the visualization process. The information output on the drivers is related to the row reading sequence (the 1st row read is output on R0, the 2nd on R1 and so on) ...
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... SET 2nd Sector Start Address SET Driver in Normal Mode (PE=0) END OF PARTIAL DISPLAY CONFIG. SECTION2 Icon Row Icon Row Icon Row Icon Row Icon Row Icon Row Icon Row Icon Row STE2004 OPTIONAL1 OPTIONAL RESET STATE 000 39/66 ...
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... STE2004 6 ID-NUMBER The STE2004 allows to program a Driver Identification Number (ID-Number). This make possible to easily manage on one platform more than one LCD module with different configuration parameters. Four are the device ID-Numbers programmable: 00111100, 00111101, 0011110 & 0011111. All have in common the first 6 bits (001111). The two least significant bit could be set connecting the SA0 and SA1 inputs to a VSS or VDD1 ...
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... PDC Partial Display Config Sector Start Address Sector Start Address Scrolling Pointer Reset 1 X Not Used X X Not Used T1 T0 Set Temperature Coefficient for V N-Line Inversion Y-CARRIAGE RETURN X CARRIAGE RETURN STE2004 LDC LDC 41/66 ...
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... STE2004 Table 12. Explanations of Table 3 & 4 symbols BIT 0 DIR Scroll by one down H[0] Select page 0 PD Device fully working V Horizontal addressing MX Normal X axis addressing MY Image is displayed not vertically mirrored DO MSB on TOP PE Partial Display disabled MUX MUx 65 Mode R Read ID-Number / I2C Address Table 13. PAGE SELECTION ...
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... VLCD temperature Coefficient 7 DESCRIPTION VLCD temperature Coefficient 0 VLCD temperature Coefficient 2 VLCD temperature Coefficient 3 VLCD temperature Coefficient 6 DESCRIPTION Multiplication Factor X2 Multiplication Factor X3 Multiplication Factor X4 Multiplication Factor X5 NOT USED NOT USED NOT USED AUTOMATIC STE2004 RESET STATE 01 RESET STATE 000 RESET STATE 00 RESET STATE 000 43/66 ...
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... STE2004 Table 21. BIAS RATIO BS2 BS1 BS0 Table 22. Y CARRIAGE RETURN REGISTER Y-C[3] Y-C[2] Y-C[1] Y-C[ Table 23. PARTIAL DISPLAY CONFIGURATION ...
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... SDAOUT SDAIN RES SCL SDA STE2004 CS SCLK SDIN SDOUT RES SCLK SD SLAVE CS CS RES D/C SCLK SDIN SDOUT D/C SCLK SD SLAVE CS SDAOUT SDAIN LR0214 NOTE: MASTER and SLAVE I2C AADDRESS MUST BE DIFFERENT STE2004 CS SCLK SDIN SDOUT LR0215 STE2004 D/C CS SCLK SDIN SDOUT LR0216 STE2004 45/66 ...
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... SDOUT SDIN-SDAIN SDAOUT VSSAUX R D/C CS RES VDD2 ANALOG VDD VDD1 DIGITAL VDD ICON VDD1 / VSSAUX SEL1 VSSAUX SEL2 SEL3 EXT_SET VDD1 / VSSAUX M/S VDD1 SA0 VDD1 / VSSAUX SA1 VDD1 / VSSAUX VSSAUX TEST VREF VSENSE_SLAVE OSC_IN FR_IN VDD1_AUX STE2004 D/C RW-RD E-WR D7-D0 CS LR0217 8 LINES P LR0110 ...
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... SDIN-SDAIN SDAOUT VSSAUX R D/C CS RES VDD2 ANALOG VDD VDD1 DIGITAL VDD ICON VDD1 / VSSAUX SEL1 VSSAUX SEL2 VDD1 SEL3 VSSAUX EXT_SET VDD1 / VSSAUX M/S VDD1 SA0 VDD1 / VSSAUX SA1 VDD1 / VSSAUX VSSAUX TEST VREF VSENSE_SLAVE OSC_IN FR_IN VDD1_AUX STE2004 LR0111 LR0112 47/66 ...
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... STE2004 Figure 62. Host Processor Interconnection with 3-line Serial Interface STE2004 Figure 63. Host Processor Interconnection with 8080-series Parallel Interface STE2004 48/66 VSS TEST_MODE P VSSAUX SCLK-SCL SDOUT SDIN-SDAIN SDAOUT VSSAUX R D/C CS RES VDD2 ANALOG VDD VDD1 DIGITAL VDD ICON ...
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... SDOUT SDIN-SDAIN SDAOUT VSSAUX R D/C CS RES VDD2 ANALOG VDD VDD1 DIGITAL VDD ICON VDD1 / VSSAUX SEL1 VDD1 SEL2 VSSAUX SEL3 VDD1 EXT_SET VDD1 / VSSAUX M/S VDD1 SA0 VDD1 / VSSAUX SA1 VDD1 / VSSAUX VSSAUX TEST VREF VSENSE_SLAVE OSC_IN FR_IN VDD1_AUX STE2004 LR0115 49/66 ...
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... STE2004 Figure 65. Application Schematic using the Internal LCD Voltage Generator and two separate supplies V DD2 Figure 66. Application Schematic using the Internal LCD Voltage Generator and a single supply 50/66 I/O VDD2 V VDD1 DD1 1 F VSS VLCDSENSE VLCD ...
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... Figure 67. Power-ON timing diagram VDD2 VDD1 RES CS SCLK SDIN D HOST DRIVER SCL- SDAIN SDOUT - SDA OUT OSCIN, FR_IN (HOST) OSC OUT, FR_OUT (DRIVER vdd Tw(res) logic(res) Hi-Z Hi-Z POWER ON RESET BOOSTER INTERNAL Acceptance OFF RESET Time STE2004 LR0208 51/66 ...
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... STE2004 Figure 68. Power-OFF timing diagram VDD2 VDD1 RES CLK-SCL SDIN-SDAIN D R HOST DRIVER SDOUT SDA-OUT OSCIN (HOST) OSC OUT FR_OUT (DRIVER) FR_IN 52/66 T VDD Hi-Z Hi-Z RESET TABLE LOADED LR0207 ...
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... Vop[6:0] - PRS[1;0]) SET Bias Raio for Normal Display Operation (BS[2:0]) SET Temperature Compensation for Normal Display Operation (T[2:0] or TC[1:0]) SET Multiplexing Rate M[1:0) SET Charge Pump for Normal Display Operation (CP[1:0]) Switch "ON" Booster and Display Control Logic (PD=0) END OF NORMAL DISPLAY MODE CONFIG. STE2004 LR0218 53/66 ...
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... STE2004 Figure 70. DATA RAM to display Mapping DISPLAY DATA RAM bank 0 bank 1 bank 2 bank 3 bank 7 bank 8 Table 25. Test Pin Configuration Test Pin TEST_VREF TEST_MODE 54/66 LCD ICOR ROW D00IN1155 Pin Configuration OPEN GND GLASS TOP VIEW DISPLAY DATA RAM = "1" DISPLAY DATA RAM = "0" ...
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... Power down Mode with internal or External VLCD. Note 4 V =2.8V; V =10V;no DD LCD display load sclk T = 25°C; note 3. amb IOH=-500 A IOL=+500 A STE2004 Value Unit - + 0.5 V DD1 - ...
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... STE2004 Table 23 Electrical Characteristics (continued) DC OPERATION (continued 1 1.75 to 4.5 V; Vss1,2 = 0V; VLCD = 4 Tamb =-40 to 85°C; unless otherwise specified) DD1 DD2 Symbol Parameter Logic Inputs V Logic LOW voltage level IL V Logic HIGH Voltage Level IH I Input Current in Logic Inputs/Outputs V Logic LOW voltage level ...
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... I/O (DRIVER) INTERFACE OUTPUT OSCIN FR_IN (HOST) OSC OUT FR_OUT (DRIVER) Test Condition V = 2.8V; DD Tamb = -20 to +70 °C fosc or fext = 72 kHz; note 1 Tw(res) Tlogic(res) Hi-Z Hi-Z RESET TABLE LOADED STE2004 Min. Typ. Max. Unit kHz 20 100 kHz LR0209 57/66 ...
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... STE2004 Table 23 Electrical Characteristics (continued) AC OPERATION (continued) (VDD1 = 1.7 to 3.6 V; VDD2 = 1.75 to 4.5 V; Vss1,2 = 0V; VLCD = 4 Tamb =-40 to 85°C; unless otherwise specified) Symbol Parameter BUS INTERFACE (See note SCL Clock Frequency SCL T Set-up time (repeated) START SU;STA Condition T Hold Time (repeated) START HD ...
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... SU( CLR CLW t SU1 t SU2 Min. Typ. Max. 125 H(A) t CYC EWLR EWLW (A) t CYC CHR CHW STE2004 Unit 59/66 ...
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... STE2004 Table 23 Electrical Characteristics (continued) AC OPERATION (continued) (VDD1 = 1.7 to 3.6 V; VDD2 = 1.75 to 4.5 V; Vss1,2 = 0V; VLCD = 4 Tamb =-40 to 85°C; unless otherwise specified) Symbol Parameter SERIAL INTERFACE F Clock Frequency SCLK T Clock Cycle SCLK CYC T SCLK pulse width HIGH PWH1 T SCLK Pulse width LOW PWL1 ...
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... C44 -596.5 C45 -596.5 C46 -596.5 C47 -596.5 C48 -596.5 C49 -596.5 C50 -596.5 C51 -596.5 C52 -596.5 C53 -596.5 C54 -596.5 C55 STE2004 PAD -1375.0 -596.5 33 -1325.0 -596.5 34 -1275.0 -596.5 35 -1225.0 -596.5 36 -1175.0 -596.5 37 -1125.0 -596.5 38 -1075.0 -596 ...
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... STE2004 Table 28. Pad Coordinates (continued) NAME PAD C56 63 375.0 C57 64 425.0 C58 65 475.0 C59 66 525.0 C60 67 575.0 C61 68 625.0 C62 69 675.0 C63 70 725.0 C64 71 775.0 C65 72 825.0 C66 73 875.0 C67 74 925.0 C68 75 975.0 C69 76 1025.0 C70 77 1075.0 C71 78 1125.0 C72 79 1175 ...
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... 596.5 VSSAUX 596.5 SDAOUT 596.5 SDIN-SDAIN 596.5 SDOUT 596.5 SCLK-SCL 596.5 D7 596.5 D6 596 596.5 596.5 D3 STE2004 PAD 156 1475.0 596.5 157 1425.0 596.5 158 1375.0 596.5 159 1325.0 596.5 160 1275.0 596.5 161 1225.0 596.5 162 1175 ...
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... STE2004 Table 28. Pad Coordinates (continued) NAME PAD 187 -675.0 D1 188 -725.0 D0 189 -775.0 VSSAUX 190 -825.0 TEST_MODE 191 -1225.0 VSS 192 -1275.0 VSS 193 -1325.0 VSS 194 -1375.0 VSS 195 -1425.0 VSS 196 -1475.0 VSS 197 -1525.0 VSS 198 -1575.0 ...
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... Table 31. Die Mechanical Dimensions Die Size ( Wafers Thickness 3 Moved the value of FSCLK parameter from Min. to Max. on the page 60/ 66. 4 Inserted Table 24 -N-Line Inversion in the page 44/66 Bump Dimensions Number 17 107 m 6.42mm x 1.46mm 500 m Description of Changes STE2004 65/66 ...
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... STE2004 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice ...