PM4328-PI PMC-Sierra, Inc., PM4328-PI Datasheet - Page 17
PM4328-PI
Manufacturer Part Number
PM4328-PI
Description
Framer, T1|E1|T3 Standard Format, 324-BGA
Manufacturer
PMC-Sierra, Inc.
Datasheet
1.PM4328-PI.pdf
(250 pages)
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PM4328-PI
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STANDARD PRODUCT
DATASHEET
PMC-2011596
PROPRIETARY AND CONFIDENTIAL
· Extracts 4-bit codewords from the E1 national use bits as specified in
· V5.2 link indication signal detection.
· Provides performance monitoring counters sufficiently large as to allow
· Provides a two-frame elastic store buffer for backplane rate adaptation that
· Frames to the E1 signaling multiframe alignment when enabled and extracts
· Can be programmed to generate an interrupt on change of signaling state.
· Provides trunk conditioning which forces programmable trouble code
· A pseudo-random sequence user selectable from 2
· Line side interface is the DS3 interface mutiplexed as per the G.747
· System side interface is either serial clock and data or H-MVIP.
· Provides external access for up to two de-jittered recovered E1 clocks.
Each one of 28 T1 transmitter sections:
· May be timed to its associated receive clock (loop timing) or may derive its
· Provides minimum ones density through Bell (bit 7), GTE or “jammed bit 8”
ETS 300 233.
performance monitor counter polling at a minimum rate of once per second.
Optionally, updates the performance monitoring counters and interrupts the
microprocessor once per second, timed to the receive line.
performs controlled slips and indicates slip occurrence and direction.
channel associated signaling. Alternatively, a common channel signaling data
link may be extracted from timeslot 16.
substitution and signaling conditioning on all channels or on selected
channels.
be detected in the E1 stream in either the ingress or egress directions. The
detector counts pattern errors using a 24-bit non-saturating PRBS error
counter. The pseudo-random sequence can be the entire E1 or any
combination of timeslots within the framed E1.
recommendation.
timing from a common egress clock or a common transmit clock; the transmit
line clock may be synthesized from an N*8kHz reference.
zero code suppression on a per-DS0 basis.
ISSUE 1
4
11
–1, 2
15
HIGH DENSITY T1/E1 FRAMER
–1 or2
AND M13 MULTIPLEXER
PM4328 TECT3
20
–1, may
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