IDT72T72115 Integrated Device Technology, IDT72T72115 Datasheet - Page 52

• Manufacturer Part Number: IDT72T72115
• Description: 128k X 72 Terasync Fifo, 2.5v - Best Value!
• Manufacturer: Integrated Device Technology

DEPTH EXPANSION CONFIGURATION (FWFT MODE ONLY)
greater than 16,384, 32,768 for the IDT72T7295, 65,536 for the IDT72T72105
and 131,072 for the IDT72T72115 with an 72-bit bus width. In FWFT mode,
the FIFOs can be connected in series (the data outputs of one FIFO connected
to the data inputs of the next) with no external logic necessary. The resulting
configuration provides a total depth equivalent to the sum of the depths
associated with each single FIFO. Figure 37 shows a depth expansion using
two IDT72T7285/72T7295/72T72105/72T72115 devices.
in the depth expansion configuration. The first word written to an empty
configuration will pass from one FIFO to the next ("ripple down") until it finally
appears at the outputs of the last FIFO in the chain – no read operation is
necessary but the RCLK of each FIFO must be free-running. Each time the
data word appears at the outputs of one FIFO, that device's OR line goes LOW,
enabling a write to the next FIFO in line.
the last FIFO in the chain to go LOW (i.e. valid data to appear on the last FIFO's
outputs) after a word has been written to the first FIFO is the sum of the delays
for each individual FIFO:
where N is the number of FIFOs in the expansion and T
period. Note that extra cycles should be added for the possibility that the t
IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync™ ™ ™ ™ ™ 72-BIT FIFO
16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72
FWFT/SI
WRITE ENABLE
DATA IN
WRITE CLOCK
INPUT READY
The IDT72T7285 can easily be adapted to applications requiring depths
Care should be taken to select FWFT mode during Master Reset for all FIFOs
For an empty expansion configuration, the amount of time it takes for OR of
n
Figure 37. Block Diagram of 32,768 x 72, 65,536 x 72, 131,072 x 72 and 262,144 x 72 Depth Expansion
(N – 1)*(4*transfer clock) + 3*T
Dn
WEN
IR
WCLK
72T72105
72T72115
FWFT/SI
72T7285
72T7295
IDT
TRANSFER CLOCK
RCLK
REN
RCS
RCLK
OE
OR
Qn
RCLK
is the RCLK
SKEW1
GND
n
52
specification is not met between WCLK and transfer clock, or RCLK and transfer
clock, for the OR flag.
depth expansion configuration. There will be no delay evident for subsequent
words written to the configuration.
configuration will "bubble up" from the last FIFO to the previous one until it finally
moves into the first FIFO of the chain. Each time a free location is created in one
FIFO of the chain, that FIFO's IR line goes LOW, enabling the preceding FIFO
to write a word to fill it.
FIFO in the chain to go LOW after a word has been read from the last FIFO is
the sum of the delays for each individual FIFO:
where N is the number of FIFOs in the expansion and T
period. Note that extra cycles should be added for the possibility that the t
specification is not met between RCLK and transfer clock, or WCLK and transfer
clock, for the IR flag.
is faster. Both these actions result in data moving, as quickly as possible, to the
end of the chain and free locations to the beginning of the chain.
The "ripple down" delay is only noticeable for the first word written to an empty
The first free location created by reading from a full depth expansion
For a full expansion configuration, the amount of time it takes for IR of the first
The Transfer Clock line should be tied to either WCLK or RCLK, whichever
WCLK
IR
Dn
WEN
(N – 1)*(3*transfer clock) + 2 T
72T72105
72T72115
FWFT/SI
72T7285
72T7295
IDT
COMMERCIAL AND INDUSTRIAL
RCLK
REN
RCS
OR
TEMPERATURE RANGES
OE
Qn
READ CHIP SELECT
OUTPUT ENABLE
n
WCLK
OUTPUT READY
WCLK
READ ENABLE
READ CLOCK
DATA OUT
5994 drw42
is the WCLK
SKEW1