MCP9802 Microchip Technology Inc., MCP9802 Datasheet - Page 16

• Manufacturer Part Number: MCP9802
• Description: 2-wire High-accuracy Temperature Sensor
• Manufacturer: Microchip Technology Inc.

MCP9800/1/2/3
5.0
5.1
The MCP9800/1/2/3 serial clock input (SCLK) and the
bidirectional serial data line (SDA) form a 2-Wire
bidirectional serial port for communication.
The following bus protocol has been defined:
TABLE 5-1:
5.1.1
Data transfers are initiated by a start condition
(START), followed by a 7-bit device address and a 1-bit
read/write. Acknowledge (ACK) from slave confirms
the reception of each byte. Each access must be
terminated by a stop condition (STOP).
Data transfer may be initiated when the bus is in IDLE.
DS21909B-page 16
Transmitter Device sending data to the bus
Receiver
Master
Slave
START
STOP
Read/Write A read or write to the MCP9800/1/2/3
ACK
NAK
Busy
Not Busy
Data Valid
Term
SERIAL COMMUNICATION
2-Wire I
Interface
DATA TRANSFER
Device receiving data from the bus
The device that controls the serial bus,
typically a microcontroller
The device addressed by the master,
such as the MCP9800/1/2/3
A unique signal from master to initiate
serial interface with a slave
A unique signal from the master to
terminate serial interface from a slave
registers
A receiver Acknowledges (ACK) the
reception of each byte by polling the
bus
A receiver Not-Acknowledges (NAK) or
releases the bus to show End-of-Data
(EOD)
Communication is not possible
because the bus is in use
The bus is in the idle state, both SDA
and SCLK remain high
SDA must remain stable before SCLK
becomes high in order for a data bit to
be considered valid. During normal
data transfers, SDA only changes state
while SCLK is low
MCP980X SERIAL BUS
CONVENTIONS
2
C/SMBus Compatible
Description
5.1.2
The bus is controlled by a master device (typically a
microcontroller) that controls the bus access and gener-
ates the start and stop conditions. The MCP9800/1/2/3
is a slave device and does not control other devices in
the bus. Both master and slave devices can operate as
either transmitter or receiver. However, the master
device determines which mode is activated.
5.1.3
A high-to-low transition of the SDA line (while SCLK is
high) is the start condition. All data transfers must be
preceded by a start condition from the master. If a start
condition is generated during data transfer, the
MCP9800/1/2/3 resets and accepts the new start
condition.
A low-to-high transition of the SDA line (while SCLK is
high) is the stop condition. All data transfers must be
ended by a stop condition from the master. If a stop
condition is introduced during data transmission, the
MCP9800/1/2/3 releases the bus.
5.1.4
Following the start condition, the host must transmit the
address byte to the MCP9800/1/2/3. The 7-bit address
for the MCP9800/02A0 and MCP9800/02A5 is
<1001000> and <1001101> in binary, respectively.
The
<1001,A2,A1,A0> in binary, where the A0, A1 and A2
bits are set externally by connecting the corresponding
pins to V
mitted in the serial bit stream must match the selected
address for the MCP9800/1/2/3 to respond with an
ACK.
Bit 8 in the address byte is a read/write bit. Setting this
bit to ‘1’ commands a read operation, while ‘0’
commands a write operation.
FIGURE 5-1:
SCLK
SDA
address
DD
Start
MASTER/SLAVE
START/STOP CONDITION
ADDRESS BYTE
<1> or GND <0>. The 7-bit address trans-
1
1
Address
Code
2
0
for
3
0
Device Addressing.
 2004 Microchip Technology Inc.
Address Byte
4
1 A2 A1 A0
the
5
Address
Slave
MCP9800/1/2/3 Response
6
7
MCP9802/03
R/W
8
9
A
C
K
is