MCP6S22 Microchip Technology Inc., MCP6S22 Datasheet - Page 4
![no-image](/images/manufacturer_photos/0/4/440/microchip_technology_inc__sml.jpg)
MCP6S22
Manufacturer Part Number
MCP6S22
Description
Single-ended, Rail-to-rail I/o, Low Gain Pga
Manufacturer
Microchip Technology Inc.
Datasheet
1.MCP6S22.pdf
(43 pages)
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCP6S22-I/MS
Manufacturer:
Microchip Technology
Quantity:
135
Company:
Part Number:
MCP6S22-I/MS
Manufacturer:
MICROCHIP
Quantity:
12 000
Part Number:
MCP6S22-I/MS
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
Company:
Part Number:
MCP6S22-I/P
Manufacturer:
MICROCHIP
Quantity:
12 000
Company:
Part Number:
MCP6S22-I/SN
Manufacturer:
MICROCHIP
Quantity:
12 000
Part Number:
MCP6S22-I/SN
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
Part Number:
MCP6S22DM-PICTL
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
Company:
Part Number:
MCP6S22T-I/SN
Manufacturer:
MICROCHIP
Quantity:
12 000
Part Number:
MCP6S22T-I/SN
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
MCP6S21/2/6/8
DIGITAL CHARACTERISTICS
DS21117A-page 4
Electrical Specifications: Unless otherwise indicated, T
Input = CH0 = (0.3V)/G, CH1 to CH7 = 0.3V, R
SPI Inputs (CS, SI, SCK)
Logic Threshold, Low
Input Leakage Current
Logic Threshold, High
Amplifier Output Leakage Current
SPI Output (SO, for MCP6S26 and MCP6S28)
Logic Threshold, Low
Logic Threshold, High
SPI Timing
Pin Capacitance
Input Rise/Fall Times (CS, SI, SCK)
Output Rise/Fall Times (SO)
CS high time
SCK edge to CS fall setup time
CS fall to first SCK edge setup time
SCK Frequency
SCK high time
SCK low time
SCK last edge to CS rise setup time
CS rise to SCK edge setup time
SI set-up time
SI hold time
SCK to SO valid propagation delay
CS rise to SO forced to zero
Channel and Gain Select Timing
Channel Select Time
Gain Select Time
Shutdown Mode Timing
Out of Shutdown mode (CS goes
high) to Amplifier Output Turn-on
Time
Into Shutdown mode (CS goes high)
to Amplifier Output High-Z Turn-off
Time
POR Timing
Power-On Reset power-up time
Power-On Reset power-down time
Note 1: Not tested in production. Set by design and characterization.
2: When using the device in the daisy chain configuration, maximum clock frequency is determined by a combination of
propagation delay time (t
fall times of 5 ns. Maximum f
Parameters
DO
SCK
80 ns), data input setup time (t
t
t
Sym
C
t
t
t
t
V
CSSC
f
SCCS
t
t
V
t
t
t
V
RFO
CSH
SCK
t
t
t
SOZ
t
t
RPU
RPD
V
CS0
t
CS1
OFF
t
I
—
RFI
LO
SU
HD
DO
CH
t
ON
OH
PIN
HI
IL
OL
G
is, therefore,
IL
IH
L
= 10 k to V
V
0.7V
DD
Min
-1.0
-1.0
V
100
40
10
40
40
40
30
40
10
—
—
—
—
—
—
—
—
—
—
—
—
0
SS
-0.5
A
DD
= +25°C, V
5.8 MHz.
DD
/2, C
Typ
1.5
3.5
1.5
10
30
10
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
5
1
L
DD
= 60 pF, SI and SCK are tied low, and CS is tied high.
SU
V
0.3V
= +2.5V to +5.5V, V
SS
Max
+1.0
+1.0
V
V
10
80
80
10
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
DD
DD
2
+0.4
40 ns), SCK high time (t
DD
Units
MHz
µA
µA
pF
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
µs
µs
µs
µs
µs
V
V
V
V
In Shutdown mode
I
I
All digital I/O pins
Note 1
MCP6S26 and MCP6S28
SCK edge when CS is high
V
SCK edge when CS is high
MCP6S26 and MCP6S28
MCP6S26 and MCP6S28
CHx = 0.6V, CHy =0.3V, G = 1,
CHx to CHy select
CS = 0.7V
CHx = 0.3V, G = 5 to G = 1 select,
CS = 0.7V
CS = 0.7V
CS = 0.7V
V
50% V
V
50% V
OL
OH
SS
DD
DD
DD
= 2.1 mA, V
= -400 µA
= GND, V
= 5V (Note 2)
= V
= V
DD
DD
POR
POR
2003 Microchip Technology Inc.
DD
DD
HI
DD
to 90% V
to 90% V
DD
to V
to V
- 0.1V to V
+ 0.1V to V
to V
to V
Conditions
40 ns), and SCK rise and
REF
DD
OUT
OUT
OUT
OUT
= V
= 5V
OUT
OUT
90% point
90% point
90% point
90% point
SS
POR
point
point
POR
, G = +1 V/V,
+ 0.1V,
- 0.1V,