ATA6020N ATMEL Corporation, ATA6020N Datasheet - Page 43

• Manufacturer Part Number: ATA6020N
• Description: Low-current Microcontroller For Watchdog Function
• Manufacturer: ATMEL Corporation

5.2.7.3
4708D–4BMCU–09/05
General SSI Operation
The SSI is comprised essentially of an 8–bit shift register with two associated 8-bit buffers - the
receive buffer (SRB) for capturing the incoming serial data and a transmit buffer (STB) for inter-
mediate storage of data to be serially output. Both buffers are directly accessable by software.
Transferring the parallel buffer data into and out of the shift register is controlled automatically by
the SSI control, so that both single byte transfers or continuous bit streams can be supported.
The SSI can generate the shift clock (SC) either from one of several on-chip clock sources or
accept an external clock. The external shift clock is output on, or applied to the Port BP40.
Selection of an external clock source is performed by the Serial Clock Direction control bit
(SCD). In the combinational modes, the required clock is selected by the corresponding timer
mode.
The SSI can operate in three data transfer modes – synchronous 8-bit shift mode, a 9-bit Multi-
Chip Link mode (MCL), containing 8-bit data and 1-bit acknowledge, and a corresponding 8-bit
MCL mode without acknowledge. In both MCL modes the data transmission begins after a valid
start condition and ends with a valid stop condition.
External SSI clocking is not supported in these modes. The SSI should thus generate and have
full control over the shift clock so that it can always be regarded as an MCL-bus master device.
All directional control of the external data port used by the SSI is handled automatically and is
dependent on the transmission direction set by the Serial Data Direction (SDD) control bit. This
control bit defines whether the SSI is currently operating in transmit (TX) mode or receive (RX)
mode.
Serial data is organized in 8-bit telegrams which are shifted with the most significant bit first. In
the 9-bit MCL mode, an additional acknowledge bit is appended to the end of the telegram for
handshaking purposes (see “MCL protocol”).
At the beginning of every telegram, the SSI control loads the transmit buffer into the shift register
and proceeds immediately to shift data serially out. At the same time, incoming data is shifted
into the shift register input. This incoming data is automatically loaded into the receive buffer
when the complete telegram has been received. Data can, if required thus be simultaneously
received and transmitted.
Before data can be transferred, the SSI must first be activated. This is performed by means of
the SSI reset control (SIR) bit. All further operation then depends on the data directional mode
(TX/RX) and the present status of the SSI buffer registers shown by the Serial Interface Ready
Status Flag (SRDY). This SRDY flag indicates the (empty/full) status of either the transmit buffer
(in TX mode), or the receive buffer (in RX mode). The control logic ensures that data shifting is
temporarily halted at any time, if the appropriate receive/transmit buffer is not ready (SRDY = 0).
The SRDY status will then automatically be set back to “1” and data shifting resumed as soon as
the application software loads the new data into the transmit register (in TX mode) or frees the
shift register by reading it into the receive buffer (in RX mode).
A further activity status (ACT) bit indicates the present status of serial communication. The ACT
bit remains high for the duration of the serial telegram or if MCL stop or start conditions are cur-
rently being generated. Both the current SRDY and ACT status can be read in the SSI status
register. To deactivate the SSI, the SIR bit must be set high.
ATA6020N
43