ATA3741 ATMEL Corporation, ATA3741 Datasheet
ATA3741
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ATA3741 Summary of contents
Page 1
... Different IF Bandwidth Versions are Available (300 kHz and 600 kHz) 1. Description The ATA3741 is a multi-chip PLL receiver device supplied in an SO20 package. It has been specially developed for the demands of RF low-cost data transmission systems with low data rates from 1 kBaud to 10 kBaud (1 kBaud to 3.2 kBaud for FSK) in Manchester or Bi-phase code ...
Page 2
... System Block Diagram Remote control transmitter 1 Li cell Encoder ATARx9x Keys Figure 1-2. Block Diagram FSK/ASK CDEM AVCC SENS AGND DGND MIXVCC LNAGND LNA_IN ATA3741 2 UHF ASK/FSK U2741B PLL Antenna Antenna XTO VCO Power amp. FSK/ASK DEMOD_OUT Demodulator and data filter Limiter out RSSI ...
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... Low: polling mode off (sleep mode) High: polling mode on (active mode) 20 DATA Data output/configuration input 4899B–RKE–10/06 Pinning SO20 SENS 1 FSK/ASK 2 CDEM 3 AVCC 4 AGND 5 DGND 6 MIXVCC 7 LNAGND 8 LNA_IN ATA3741 20 DATA 19 ENABLE 18 TEST 17 POUT 16 MODE 15 DVCC 14 XTO 13 LFGND LFVCC 3 ...
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... LF is limited. If the capacitive load is exceeded, a bit check may no longer be possible since f not settle before the bit check starts to evaluate the incoming data stream. Therefore, self polling also will not work . ATA3741 4 for the mixer ...
Page 5
... LNA_IN. The input impedance of LNA_IN is specified in 23. The parasitic board inductances and capacitances also influence the input matching. The RF receiver ATA3741 exhibits its highest sensitivity at the best signal-to-noise ratio in the LNA. Hence, noise matching is the best choice for designing the transformation network. ...
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... TOKO LL2012 47n L2 TOKO LL2012 F82NJ 1 B3551 IN 82n 2 IN_GND OUT_GND C2 CASE_GND 315 MHz 33p 25n RF IN 100p 3.3p 39n TOKO LL2012 F39NJ (Figure 3-2 and Figure 3-3), the bond wire inductivity C17 22p F47NJ 5 OUT 6 LNAGND ATA3741 LNA_IN 4899B–RKE–10/06 ...
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... VS or GND via a microcontroller or by the digital output port POUT of Sense the ATA3741 receiver IC. The receiver can be switched from full sensitivity to reduced sensitivity or vice versa at any time. In polling mode, the receiver will not wake up if the RF input signal does not exceed the selected sensitivity. If the receiver is already active, the data stream at pin DATA will disappear when the input signal is lower than defined by the reduced sensitivity ...
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... BR_Range is defined in the OPMODE register (Section Receiver” on page The ATA3741 is designed to operate with data coding where the DC level of the data signal is 50%. This is valid for Manchester and Bi-phase coding. If other modulation schemes are used, the DC level should always remain within the range of VDC_min = 33% and VDC_max = 66%. ...
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... When designing the system in terms of receiving bandwidth, the LO deviation must be consid- ered as it also determines the IF center frequency. The total LO deviation is calculated to be the sum of the deviation of the crystal and the XTO deviation of the ATA3741. Low-cost crystals are specified to be within ±100 ppm. The XTO deviation of the ATA3741 is an additional deviation due to the XTO circuit. This deviation is specified to be ± ...
Page 10
... Other applications (T Clk is given as a function of T The clock cycle of some function blocks depends on the selected baud rate range (BR_Range) which is defined in the OPMODE register. This clock cycle T mulas for further reference: BR_Range = ATA3741 10 Generation of the Basic Clock Cycle T Clk Divider :14/:10 f ...
Page 11
... The sleep time is always extended implies the temporary extension factor. The extended sleep time is used as long Table 5-6 on page 19, the highest register value of Sleep sets the receiver to a per- ATA3741 = I . During the start-up period Soff ...
Page 12
... Sleep mode through an OFF command via pin DATA or ENABLE SON OFF command Figure 5-3. Timing Diagram for a Completely Successful Bit Check Number of Checked Bits: 3 Enable IC Bit check Dem_out DATA Polling mode ATA3741 12 Sleep: X 1024 T X Sleep Clk Sleep T Clk ) Startup T Startup ...
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... Lim_min 1/f Sig t ee lim_min lim_max . Using preburst patterns that contain vari- ee and T Lim_min , defined in Section DATA_H_min 10. The maximum value of ATA3741 in the OPMODE is set to a Bitcheck shows an exceeds Lim_max and T . Lim_min Lim_max The Lim_max XClk “Receiving Mode” ...
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... Timing Diagram for Failed Bit Check (Condition: CV_Lim (Lim_min = 14, Lim_max = 24) Enable IC Bit check Dem_out Bit check 0 counter Startup Mode ATA3741 14 5-5, Figure 5-6 and Figure 5-7 illustrate the bit check for the default bit-check limits . The output of the ASK/FSK demodulator (Dem_out) is undefined during Startup ...
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... Bitcheck , the receiver switches to receiving Bitcheck of the Data signal result, is always between the specified bit-check limits, the ee = tmin1 outside that bit check limit, DATA_min ee . This function ensures a DATA_L_max ATA3741 depends Bitcheck thereby Bitcheck T . This ee DATA_min DATA_L_max Figure 15 ...
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... Figure 5-12 on page 17 pulse, the sleep time T held to “L”. If the receiver is polled exclusively by a microcontroller, T “0” to enable an instantaneous response time. This command is the faster option than via pin DATA, but at the cost of an additional connection to the microcontroller. ATA3741 16 CV_Lim < Lim_max tmin1 t ee CV_Lim < ...
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... Configuration of the Receiver The ATA3741 receiver is configured via two 12-bit RAM registers called OPMODE and LIMIT. The registers can be programmed by means of the bi-directional DATA port. If the register con- tents have changed due to a voltage drop, this condition is indicated by a certain output pattern called reset marker (RM) ...
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... Table 5-4. Effect of the Configuration Word N N Bitcheck BitChk1 BitChk0 ATA3741 18 through Table 5-9 on page 20 illustrate the effect of the individual configuration words. Lim_min Bit6 Bit7 Bit8 N V Bitcheck POUT BitChk0 POUT Sleep4 Sleep3 Lim_min 1 ...
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... Sleep X SleepTemp ATA3741 0 (Default) 1 Start Value for Sleep Counter (T = Sleep X 1024 T Sleep Sleep 2 ms for US/European applications) Sleep 22.96 ms, Europe 23.31 ms) (Default) Sleep Sleep . . . (Permanent sleep mode) Extension Factor for Sleep Time ...
Page 20
... Conservation of the Register Information The ATA3741 has integrated power-on reset and brown-out detection circuitry to provide a mechanism to preserve the RAM register information. Figure 5-13 on page 21 age V S the configuration registers in that condition. Once V the minimum reset period t is turned on. ...
Page 21
... Section on page By means of that mechanism, the receiver cannot lose its register information without communi- cating that condition via the reset marker RM. Figure 5-13. Generation of the Power-on Reset VS POR X DATA (ATA3741) Figure 5-14. Timing of the Register Programming Out1 (microcontroller) X DATA (ATA3741) Serial bi-directional X ...
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... Note that the capacitive load at pin DATA is limited. The resulting time constant t together with an optional external pull-up resistor should not be exceeded, to ensure proper operation. ATA3741 22 ATA3741 Internal pull-up Bi-directional resistor data line DATA DATA (ATA3741 [t1(min) is the minimum specified value for the relevant Clk T Clk Microcontroller I/O Out 1 (microcontroller) 4899B–RKE–10/06 ...
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... Sig Sig Sig 6 Sig Sig Sig 9 Sig Sig Sig ATA3741 Max. 6 450 150 –55 +125 –40 +105 10 Value 100 = 315 MHz, unless otherwise specified. 0 Variable Oscillator Max. Min. Typ 10) XTO 14) XTO 8 T Clk ...
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... POR Programming delay period t2 (Figure 5-11, Figure 5-14) Synchron- ization pulse t3 (Figure 5-11, Figure 5-14) Delay until the program window starts t4 (Figure 5-11, Figure 5-14) Programming window t5 (Figure 5-11, Figure 5-14) ATA3741 24 = 4.5V to 5.5V 433.92 MHz and 6.76438-Mhz Oscillator 4.90625-Mhz Oscillator (Mode 1) (Mode 0) Min. Typ. Max. Min. Typ. 1.0 1.0 1.0 1.8 1.0 1.8 3.2 1.8 3.2 5.6 3.2 5.6 10.0 5.6 149 ...
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... MHz, unless otherwise specified. 0 Symbol Min. Typ. IS 190 off IS 7.0 on IIP3 –28 IS –73 LORF NF 7 1.0 || 1.56 Zi LNA_IN 1.3 || 1.0 IP –40 1db P in_max ATA3741 Max. Unit µs Clk 256 T µs Clk µs Clk µs Clk T µs Clk Max. Unit 350 µA 8.6 mA dBm –57 dBm ...
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... Input sensitivity ASK 300-kHz IF filter Input sensitivity ASK 300-kHz IF filter BR_Range0 Input sensitivity ASK 300-kHz IF filter BR_Range1 Input sensitivity ASK 300-kHz IF filter BR_Range2 Input sensitivity ASK 300-kHz IF filter BR_Range3 Input sensitivity ASK 600-kHz IF filter ATA3741 26 = 4.5V to 5.5V 433.92 MHz and Test Conditions f = 432 ...
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... Ref_FSK Ref The sensitivity of the receiver is higher for higher values of f FSK BR_Range0 BR_Range1 BR_Range2 and BR_Range3 are not suitable for FSK operation ASK mode FSK mode ATA3741 = 315 MHz, unless otherwise specified. 0 Symbol Min. Typ. –108 –110 –106.5 –108.5 –110.5 – ...
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... Upper cut-off frequency data filter Minimum edge-to-edge time period of the input data signal for full sensitivity Reduced sensitivity Reduced sensitivity Reduced sensitivity Reduced sensitivity Reduced sensitivity Reduced sensitivity variation over full operating range ATA3741 28 = 4.5V to 5.5V 433.92 MHz and Test Conditions ...
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... ext POUT I = –1 mA POUT FSK selected ASK selected Idle mode Active mode Division factor = 10 Division factor = 14 Test input must always be set to LOW ATA3741 = 315 MHz, unless otherwise specified. 0 Symbol Min. Typ. 0 –3.5 P Red –6.0 –9.0 –11.0 –13.5 V 1.95 2.8 ThReset V 0 ...
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... Revision History Please note that the following page numbers referred to in this section refer to the specific revision mentioned, not to this document. Revision No. 4899B-RKE-10/06 ATA3741 30 Package Remarks SO20 2: IF bandwidth of 300 kHz, tube, Pb-free SO20 2: IF bandwidth of 300 kHz, taped and reeled, Pb-free ...
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... Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel’s products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life. © 2006 Atmel Corporation. All rights reserved. Atmel marks or trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others. Atmel Operations Memory ...