ATA5745 ATMEL Corporation, ATA5745 Datasheet - Page 38

• Manufacturer Part Number: ATA5745
• Description: Uhf Ask/fsk Receiver
• Manufacturer: ATMEL Corporation

16. Digital Timing Characteristics
All parameters refer to GND and are valid for T
Typical values are given at V
consumption, timing, and digital pin properties can be found in the specific sections of the “Electrical Characteristics”
38
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
10.1
10.2
10.3
10.4
10.5
No.
9.1
9.2
10
9
Parameters
Basic Clock Cycle of the Digital Circuitry
Basic clock cycle
Extended basic clock
cycle
Active Mode
Startup PLL
Startup signal
processing
Bit rate range
Minimum time period
between edges at pin
DATA_OUT
Edge-to-edge time
period of the data signal
for full sensitivity in
Active mode
ATA5745/ATA5746 [Preliminary]
VS3V_AVCC
Test Conditions
BR_Range_0
BR_Range_1
BR_Range_2
BR_Range_3
BR_Range_0
BR_Range_1
BR_Range_2
BR_Range_3
ASK
BR_Range =
BR_Range0
BR_Range1
BR_Range2
BR_Range3
FSK
BR_Range =
BR_Range0
BR_Range1
BR_Range2
BR_Range3
BR_Range_0
BR_Range_1
BR_Range_2
BR_Range_3
BR_Range_0
BR_Range_1
BR_Range_2
BR_Range_3
= V
VS5V
= 3V, T
amb
= –40°C to +105°C, V
amb
= 25°C, and f
Pin
24
T
RF
T
Startup_Sig_Proc
BR_Range
T
DATA_OUT_min
T
VS3V_AVCC
= 433.92 MHz unless otherwise specified. Details about current
Symbol
Startup_PLL
T
DATA_OUT
T
XDCLK
DCLK
= V
16 / f
VS5V
T
929.5
545.5
353.5
257.5
10
Min.
XDCLK
200
100
T
T
1.0
2.0
4.0
8.0
1.0
2.0
4.0
8.0
50
25
8
4
2
1
DCLK
DCLK
= 2.7V to 3.3V, and V
XTO
Typ.
16 / f
15 µs +
208
T
929.5
545.5
353.5
257.5
Max.
10.0
10.0
10.0
20.0
62.5
500
250
125
T
T
2.5
5.0
2.5
5.0
DCLK
8
4
2
1
DCLK
DCLK
VS5V
XTO
= 4.5V to 5.5V.
Kbits/s
Unit
µs
µs
µs
µs
µs
4596B–RKE–06/07
Type*
A
A
A
A
A
A
B